Sunnyvale, California
United States
28
2022-02-10
The entities that hold a legal rights for patent applications filed by inventor RAMSBEY Mark:
Mark RAMSBEY from Sunnyvale, US has applied for patents for these inventions. The list has both pending applications and granted patents:
Resistive change elements using passivating interface gaps and methods for making same
#2 | 2021-04-08Split gate charge trapping memory cells having different select gate and memory gate heights
#3 | 2019-12-19Memory first process flow and device
#4 | 2018-12-20Memory first process flow and device
#5 | 2018-11-27Three dimensional capacitor
#6 | 2017-07-06Split gate charge trapping memory cells having different select gate and memory gate heights
#7 | 2017-05-18Memory first process flow and device
#8 | 2016-10-06Memory first process flow and device
#9 | 2016-04-21Charge trapping split gate embedded flash memory and associated methods
#10 | 2015-10-08Use disposable gate cap to form transistors, and split gate charge trapping memory cells
#11 | 2015-06-25Gate formation memory by planarization
#12 | 2014-06-19Charge trapping split gate device and method of fabricating same
#13 | 2014-06-19THREE DIMENSIONAL CAPACITOR
#14 | 2014-06-19Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells
#15 | 2014-06-19Charge Trapping Split Gate Embedded Flash Memory and Associated Methods
#16 | 2014-06-19Memory first process flow and device
#17 | 2014-06-19Charge Trapping Device with Improved Select Gate to Memory Gate Isoloation
#18 | 2014-06-19Process charging protection for split gate charge trapping flash
#19 | 2014-06-19Memory gate landing pad made from dummy features
#20 | 2007-02-13LDC implant for mirrorbit to improve Vt roll-off and form sharper junction
#21 | 2007-01-16Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device
#22 | 2006-04-25ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices
#23 | 2006-02-16Method of forming narrowly spaced flash memory contact openings and lithography masks
#24 | 2006-01-24Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices
#25 | 2005-11-17Bitline implant utilizing dual poly
#26 | 2005-10-25Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen
#27 | 2005-02-15Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance
#28 | 2005-01-13PECVD silicon-rich oxide layer for reduced UV charging
802206 ⎘