KANATA
Canada
83
2015-02-12
The entities that hold a legal rights for patent applications filed by inventor KIM JIN-KI:
JIN-KI KIM from KANATA, CA has applied for patents for these inventions. The list has both pending applications and granted patents:
System and method of page buffer operation for memory devices
#2 | 2015-01-08PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY
#3 | 2014-10-23Device selection schemes in multi chip package NAND flash memory system
#4 | 2014-07-03HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE MEMORY
#5 | 2014-05-15HIERARCHICAL COMMON SOURCE LINE STRUCTURE IN NAND FLASH MEMORY
#6 | 2014-04-17Non-volatile semiconductor memory having multiple external power supplies
#7 | 2013-12-26APPARATUS AND METHODS FOR CARRYING OUT OPERATIONS IN A NON-VOLATILE MEMORY CELL HAVING MULTIPLE MEMORY STATES
#8 | 2013-12-19Non-Volatile Semiconductor Memory with Page Erase
#9 | 2013-08-08Single-strobe operation of memory devices
#10 | 2013-07-18Data storage and stackable chip configurations
#11 | 2013-07-11Device selection schemes in multi chip package NAND flash memory system
#12 | 2013-04-25Stacked semiconductor devices including a master device
#13 | 2013-03-14Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
#14 | 2013-02-07Non-volatile semiconductor memory having multiple external power supplies
#15 | 2013-01-03Independent link and bank selection
#16 | 2012-10-04Non-volatile semiconductor memory with page erase
#17 | 2012-09-20Hierarchical common source line structure in NAND flash memory
#18 | 2012-08-30NAND flash architecture with multi-level row decoding
#19 | 2012-03-15System and method of page buffer operation for memory devices
#20 | 2011-12-22Apparatus and method for using a page buffer of a memory device as a temporary cache
#21 | 2011-12-22Semiconductor device with through-silicon vias
#22 | 2011-12-22Semiconductor device with configurable through-silicon vias
#23 | 2011-11-03Non-volatile semiconductor memory with page erase
#24 | 2011-09-29Hierarchical common source line structure in NAND flash memory
#25 | 2011-08-18Non-volatile semiconductor memory having multiple external power supplies
#26 | 2011-07-21Independent link and bank selection
#27 | 2011-06-23Hybrid solid-state memory system having volatile and non-volatile memory
#28 | 2011-06-02MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM
#29 | 2011-05-12Stacked semiconductor devices including a master device
#30 | 2011-04-28Single-strobe operation of memory devices
#31 | 2011-04-14APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE
#32 | 2011-03-24Non-volatile semiconductor memory with page erase
#33 | 2011-02-10Power supplies in flash memory devices and systems
#34 | 2010-12-02Nonvolatile semiconductor memory device
#35 | 2010-10-21Apparatus and method for communicating with semiconductor devices of a serial interconnection
#36 | 2010-09-09Partial block erase architecture for flash memory
#37 | 2010-09-09NAND flash architecture with multi-level row decoding
#38 | 2010-08-26Stacked semiconductor devices including a master device
#39 | 2010-08-05Independent link and bank selection
#40 | 2010-05-13System including a plurality of encapsulated semiconductor chips
#41 | 2010-05-06Non-volatile semiconductor memory having multiple external power supplies
#42 | 2010-04-15Bridge device architecture for connecting discrete memory devices to a system
#43 | 2010-04-15Composite memory having a bridging device for connecting discrete memory devices to a system
#44 | 2010-03-18Mass data storage system with non-volatile memory modules
#45 | 2010-02-04NONVOLATILE MEMORY SYSTEM
#46 | 2009-11-12Hybrid solid-state memory system having volatile and non-volatile memory
#47 | 2009-11-12Power supplies in flash memory devices and systems
#48 | 2009-09-17Non-volatile semiconductor memory with page erase
#49 | 2009-07-23Nonvolatile memory having non-power of two memory capacity
#50 | 2009-07-23Nand flash memory access with relaxed timing constraints
#51 | 2009-07-23Memory system and method with serial and parallel modes
#52 | 2009-06-25Dual function compatible non-volatile memory device
#53 | 2009-06-25Hierarchical common source line structure in NAND flash memory
#54 | 2009-06-25Data storage and stackable configurations
#55 | 2009-06-18Semiconductor memory device suitable for interconnection in a ring topology
#56 | 2009-04-23Dynamic random access memory with fully independent partial array refresh function
#57 | 2009-04-23Single-strobe operation of memory devices
#58 | 2009-03-19Memory with output control
#59 | 2008-11-13Flash memory device with data output control
#60 | 2008-09-11Partial block erase architecture for flash memory
#61 | 2008-08-28Apparatus and method of page program operation for memory devices with mirror back-up of data
#62 | 2008-08-28System and method of page buffer operation for memory devices
#63 | 2008-08-28Apparatus and method for using a page buffer of a memory device as a temporary cache
#64 | 2008-08-21SEMICONDUCTOR DEVICE AND METHOD FOR REDUCING POWER CONSUMPTION IN A SYSTEM HAVING INTERCONNECTED DEVICES
#65 | 2008-08-21Non-volatile semiconductor memory having multiple external power supplies
#66 | 2008-08-14Apparatus and method for producing identifiers regardless of mixed device type in a serial interconnection
#67 | 2008-07-31Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
#68 | 2008-07-10Apparatus and method for communicating with semiconductor devices of a serial interconnection
#69 | 2008-06-26Hybrid solid-state memory system having volatile and non-volatile memory
#70 | 2008-06-26Apparatus and method for producing IDS for interconnected devices of mixed type
#71 | 2008-06-12Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
#72 | 2008-06-12Memory system and method with serial and parallel modes
#73 | 2008-02-28Modular command structure for memory and memory system
#74 | 2007-11-01Dynamic random access memory with fully independent partial array refresh function
#75 | 2007-10-04Apparatus and method for establishing device identifiers for serially interconnected devices
#76 | 2007-10-04Non-volatile semiconductor memory with page erase
#77 | 2007-07-19Nonvolatile memory system
#78 | 2007-07-05Memory with output control
#79 | 2007-06-21Independent link and bank selection
#80 | 2007-05-17Daisy chain cascading devices
#81 | 2007-04-05Daisy chain cascading devices
#82 | 2007-04-05Multiple independent serial link memory
#83 | 2005-03-29Differential sensing amplifier for content addressable memory
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