San Jose, California
United States
115
2026-04-23
The entities that hold a legal rights for patent applications filed by inventor Lu Jun:
Jun Lu from San Jose, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SEMICONDUCTOR PACKAGE HAVING COPPER PLATED SOURCE PADS AND METHOD OF MAKING THE SAME
#2 | 2026-01-01SEMICONDUCTOR POWER MODULE PACKAGE HAVING LEAD FRAME ANCHORED BARS
#3 | 2025-05-29CHIP SCALE PACKAGE (CSP) SEMICONDUCTOR DEVICE HAVING THIN SUBSTRATE
#4 | 2023-10-19SEMICONDUCTOR POWER MODULE PACKAGE HAVING LEAD FRAME ANCHORED BARS
#5 | 2023-09-28Chip scale package (CSP) semiconductor device having thin substrate
#6 | 2023-01-26Semiconductor package having thin substrate and method of making the same
#7 | 2022-09-01DMOS FET chip scale package and method of making the same
#8 | 2021-04-29Semiconductor package having thin substrate and method of making the same
#9 | 2019-06-20Semiconductor package having high mechanical strength
#10 | 2019-02-28Molded intelligent power module and method of making the same
#11 | 2019-01-03Molded intelligent power module for motors
#12 | 2018-04-19Molded intelligent power module and method of making the same
#13 | 2018-04-19Molded intelligent power module
#14 | 2017-06-29Power semiconductor device with small contact footprint and the preparation method
#15 | 2017-04-06Battery protection package and process of making the same
#16 | 2017-02-02Battery protection package and process of making the same
#17 | 2016-12-29Semiconductor package with small gate clip and assembly method
#18 | 2016-12-29Power semiconductor package device having locking mechanism, and preparation method thereof
#19 | 2016-10-27Hybrid packaged lead frame based multi-chip semiconductor device with multiple interconnecting structures
#20 | 2016-10-20Combined packaged power semiconductor device
#21 | 2016-09-06Dual-side exposed semiconductor package with ultra-thin die and manufacturing method thereof
#22 | 2016-08-30Power device and preparation method thereof
#23 | 2016-07-19Power semiconductor package device having locking mechanism, and preparation method thereof
#24 | 2016-06-02METHOD FOR PACKAGING A POWER DEVICE WITH BOTTOM SOURCE ELECTRODE
#25 | 2016-05-05Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
#26 | 2016-04-14Semiconductor package of a flipped MOSFET chip and a multi-based die paddle with top surface groove-divided multiple connecting areas for connection to the flipped MOSFET electrodes
#27 | 2016-04-07Embedded package and method thereof
#28 | 2016-03-31Power semiconductor device and the preparation method
#29 | 2016-03-31Semiconductor package with small gate clip and assembly method
#30 | 2016-03-22Power device and preparation method thereof
#31 | 2016-03-17Wafer process for molded chip scale package (MCSP) with thick backside metallization
#32 | 2016-02-25Power semiconductor device and preparation method thereof
#33 | 2016-02-04MCSP power semiconductor devices and preparation methods thereof
#34 | 2015-12-10Power semiconductor device with small contact footprint and the preparation method
#35 | 2015-12-10Combined packaged power semiconductor device
#36 | 2015-11-12Embedded package and method thereof
#37 | 2015-10-27Semiconductor package with small gate clip and assembly method
#38 | 2015-10-01Semiconductor device with thick bottom metal and preparation method thereof
#39 | 2015-09-03Power semiconductor device and preparation method thereof
#40 | 2015-08-27Combined packaged power semiconductor device
#41 | 2015-08-20Method of hybrid packaging a lead frame based multi-chip semiconductor device with multiple interconnecting structures
#42 | 2015-07-23Flip chip semiconductor device
#43 | 2015-07-02Preparation method of a thin power device
#44 | 2015-06-25Method of making stacked multi-chip packaging structure
#45 | 2015-06-18Semiconductor device for restraining creep-age phenomenon and fabricating method thereof
#46 | 2015-03-26Method for packaging a power device with bottom source electrode
#47 | 2015-03-19POWER SEMICONDUCTOR DEVICE PACKAGE AND FABRICATION METHOD
#48 | 2015-02-10Stacked multi-chip bottom source semiconductor device and preparation method thereof
#49 | 2015-02-05Stacked multi-chip packaging structure and manufacturing method thereof
#50 | 2015-01-22Thin power device and preparation method thereof
#51 | 2015-01-22Packaging structure of a semiconductor device
#52 | 2014-12-11Hybrid packaged lead frame based multi-chip semiconductor device with multiple semiconductor chips and multiple interconnecting structures
#53 | 2014-12-11A SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET
#54 | 2014-10-23Wafer process for molded chip scale package (MCSP) with thick backside metallization
#55 | 2014-09-18Semiconductor package and fabrication method thereof
#56 | 2014-09-18Semiconductor device with thick bottom metal and preparation method thereof
#57 | 2014-08-14Method of making a low-Rdson vertical power MOSFET device
#58 | 2014-07-15Packaging method of molded wafer level chip scale package (WLCSP)
#59 | 2014-07-10Stacked power semiconductor device using dual lead frame
#60 | 2014-06-26COPPER WIRE BONDING STRUCTURE IN SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
#61 | 2014-05-01Stacked dual-chip packaging structure and preparation method thereof
#62 | 2014-04-17Dual-leadframe multi-chip package
#63 | 2014-03-20Semiconductor packaging method using connecting plate for internal connection
#64 | 2014-03-13Semiconductor package with connecting plate for internal connection
#65 | 2014-02-27Stacked dual chip package having leveling projections
#66 | 2014-02-06Top exposed semiconductor chip package
#67 | 2013-11-21Semiconductor encapsulation method
#68 | 2013-11-14Multi-layer lead frame package and method of fabrication
#69 | 2013-10-17FABRICATION METHOD OF A MIXED ALLOY LEAD FRAME FOR PACKAGING POWER SEMICONDUCTOR DEVICES
#70 | 2013-08-29Aluminum alloy lead-frame and its use in fabrication of power semiconductor package
#71 | 2013-08-15Packaging method of molded wafer level chip scale package (WLCSP)
#72 | 2013-05-23Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process
#73 | 2013-02-28Method of making a low-Rdson vertical power MOSFET device
#74 | 2013-02-14Wafer level package structure and the fabrication method thereof
#75 | 2012-12-20Semiconductor package with adhesive material pre-printed on the lead frame and chip, and its manufacturing method
#76 | 2012-11-29Stacked power semiconductor device using dual lead frame and manufacturing method
#77 | 2012-10-04Package structure for DC-DC converter
#78 | 2012-10-04Flip chip semiconductor device
#79 | 2012-09-20Power device with bottom source electrode
#80 | 2012-08-02Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors
#81 | 2012-06-28Method of making a copper wire bond package
#82 | 2012-06-28Dual-leadframe multi-chip package and method of manufacture
#83 | 2012-06-14Top exposed package and assembly method
#84 | 2012-03-15Package structure for DC-DC converter
#85 | 2012-03-01Semiconductor package for forming a leadframe package
#86 | 2012-02-02Semiconductor encapsulation and method thereof
#87 | 2011-12-22Combined packaged power semiconductor device
#88 | 2011-11-17Stacked-die package for battery power management
#89 | 2011-09-29Dual-leadframe multi-chip package and method of manufacture
#90 | 2011-09-22Stacked dual chip package and method of fabrication
#91 | 2011-09-22Multi-layer lead frame package and method of fabrication
#92 | 2011-09-15Semiconductor packaging and fabrication method using connecting plate for internal connection
#93 | 2011-08-11Semiconductor package of a flipped MOSFET and its manufacturing method
#94 | 2011-06-02Process to form semiconductor packages with external leads
#95 | 2011-05-26Lead frame-based discrete power inductor
#96 | 2011-05-12Use of discrete conductive layer in semiconductor device to re-route bonding wires for semiconductor device package
#97 | 2011-05-12Planar grooved power inductor structure and method
#98 | 2011-05-05Power semiconductor package
#99 | 2011-04-28Method of attaching an interconnection plate to a semiconductor die within a leadframe package
#100 | 2011-03-31MIXED ALLOY LEAD FRAME FOR PACKAGING POWER SEMICONDUCTOR DEVICES AND ITS FABRICATION METHOD
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