Hsinchu,
Taiwan
85
2023-12-21
70
2025-11-18
These are the the leading inventors for applications assigned to POWERTECH TECHNOLOGY, INC.:
POWERTECH TECHNOLOGY, INC. based in Hsinchu,, TW has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
FAN-OUT PACKAGE STRUCTURE OF IMAGE SENSING DEVICE AND MANUFACTURING METHOD THEREOF
#2 | 2023-07-13 ✅ Patent 12,557,692 granted on 2026-02-17SEMICONDUCTOR PACKAGING ASSEMBLY AND SEMICONDUCTOR PACKAGING STRUCTURE
#3 | 2023-04-13FAN-OUT PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
#4 | 2022-10-13 ✅ Patent 12,154,863 granted on 2024-11-26Fan-out semiconductor package and method for manufacturing the same
#5 | 2022-04-28DEVICE FOR OVER-THE-AIR TESTING
#6 | 2022-03-31 ✅ Patent 11,658,084 granted on 2023-05-23Semiconductor packaging structure
#7 | 2022-01-13SEMICONDUCTOR COMPOSITE STRUCTURE, METHOD FOR MAKING THE SAME, AND SEMICONDUCTOR DEVICE HAVING THE SAME
#8 | 2021-12-02 ✅ Patent 11,300,636 granted on 2022-04-12Testing device for determining electrical connection status
#9 | 2021-11-11 ✅ Patent 11,302,539 granted on 2022-04-12Semiconductor packaging structure and method for packaging semiconductor device
#10 | 2021-07-15 ✅ Patent 11,587,808 granted on 2023-02-21Chip carrier device
#11 | 2021-06-24 ✅ Patent 11,367,641 granted on 2022-06-21Wafer storage device, carrier plate and wafer cassette
#12 | 2019-03-14 ✅ Patent 10,381,278 granted on 2019-08-13Testing method of packaging process and packaging structure
#13 | 2018-07-10 ✅ Patent 10,021,784 granted on 2018-07-10Electronic device and electronic circuit board thereof
#14 | 2016-06-28 ✅ Patent 9,379,043 granted on 2016-06-28TSV structure having insulating layers with embedded voids
#15 | 2016-04-28 ✅ Patent 9,419,033 granted on 2016-08-16Chip scale package of image sensor having dam combination
#16 | 2015-08-04 ✅ Patent 9,099,364 granted on 2015-08-04MPS-C2 semiconductor device having shorter supporting posts
#17 | 2015-04-02SUBSTRATELESS PACKAGES WITH SCRIBE DISPOSED ON HEAT SPREADER
#18 | 2015-03-05 ✅ Patent 9,250,288 granted on 2016-02-02Wafer-level testing method for singulated 3D-stacked chip cubes
#19 | 2015-02-19FINE-PITCH PILLAR BUMP LAYOUT STRUCTURE ON CHIP
#20 | 2015-02-19FABRICATION PROCESS AND STRUCTURE TO FORM BUMPS ALIGNED ON TSV ON CHIP BACKSIDE
#21 | 2014-06-19 ✅ Patent 8,853,834 granted on 2014-10-07Leadframe-type semiconductor package having EMI shielding layer connected to ground
#22 | 2014-02-20 ✅ Patent 8,703,508 granted on 2014-04-22Method for wafer-level testing diced multi-chip stacked packages
#23 | 2013-09-24 ✅ Patent 8,541,870 granted on 2013-09-24Semiconductor package utilizing tape to reinforce fixing of leads to die pad
#24 | 2013-03-28 ✅ Patent 8,710,859 granted on 2014-04-29Method for testing multi-chip stacked packages
#25 | 2013-03-21 ✅ Patent 8,980,694 granted on 2015-03-17Fabricating method of MPS-C2 package utilized form a flip-chip carrier
#26 | 2013-02-05 ✅ Patent 8,368,192 granted on 2013-02-05Multi-chip memory package with a small substrate
#27 | 2013-01-31 ✅ Patent 8,546,942 granted on 2013-10-01Flip-chip semiconductor device having anisotropic electrical interconnection and substrate utilized for the package
#28 | 2013-01-03 ✅ Patent 8,378,483 granted on 2013-02-19Fabrication process and device of multi-chip package having spliced substrates
#29 | 2012-12-27 ✅ Patent 8,559,252 granted on 2013-10-15Memory testing device having cross interconnections of multiple drivers and its implementing method
#30 | 2012-06-07TAPE
#31 | 2011-09-22 ✅ Patent 8,048,721 granted on 2011-11-01Method for filling multi-layer chip-stacked gaps
#32 | 2011-09-08 ✅ Patent 8,237,273 granted on 2012-08-07Metal post chip connecting device and method free to use soldering material
#33 | 2011-09-08 ✅ Patent 8,125,063 granted on 2012-02-28COL package having small chip hidden between leads
#34 | 2011-04-19 ✅ Patent 7,927,919 granted on 2011-04-19Semiconductor packaging method to save interposer
#35 | 2011-03-08 ✅ Patent 7,902,666 granted on 2011-03-08Flip chip device having soldered metal posts by surface mounting
#36 | 2011-02-01 ✅ Patent 7,879,648 granted on 2011-02-01Fabrication method for high pin count chip package
#37 | 2010-10-28 ✅ Patent 8,063,492 granted on 2011-11-22Multi-chip stacked package
#38 | 2010-10-14 ✅ Patent 7,985,662 granted on 2011-07-26Method for manufacturing dies formed with a dielectric layer
#39 | 2010-10-14 ✅ Patent 7,972,904 granted on 2011-07-05Wafer level packaging method
#40 | 2010-08-17 ✅ Patent 7,776,649 granted on 2010-08-17Method for fabricating wafer level chip scale packages
#41 | 2010-07-01 ✅ Patent 7,913,539 granted on 2011-03-29Apparatus for drop testing and method utilizing the same
#42 | 2010-05-27 ✅ Patent 8,049,339 granted on 2011-11-01Semiconductor package having isolated inner lead
#43 | 2010-05-20 ✅ Patent 8,240,029 granted on 2012-08-14Method for forming an isolated inner lead from a leadframe
#44 | 2010-05-06 ✅ Patent 8,040,690 granted on 2011-10-18Inner-connecting structure of lead frame and its connecting method
#45 | 2010-04-06 ✅ Patent 7,691,676 granted on 2010-04-06Mold array process for semiconductor packages
#46 | 2010-04-01 ✅ Patent 7,786,568 granted on 2010-08-31Window BGA semiconductor package
#47 | 2010-02-23 ✅ Patent 7,667,306 granted on 2010-02-23Leadframe-based semiconductor package
#48 | 2010-02-18 ✅ Patent 8,053,676 granted on 2011-11-08Substrate panel having a plurality of substrate strips for semiconductor packages
#49 | 2010-01-07Method for cutting large-size wafer and apparatus for the same
#50 | 2009-12-15 ✅ Patent 7,633,160 granted on 2009-12-15Window-type semiconductor package to avoid peeling at moldflow entrance
#51 | 2009-12-15 ✅ Patent 7,633,143 granted on 2009-12-15Semiconductor package having plural chips side by side arranged on a leadframe
#52 | 2009-12-10 ✅ Patent 7,919,851 granted on 2011-04-05Laminate substrate and semiconductor package utilizing the substrate
#53 | 2009-12-10 ✅ Patent 7,619,307 granted on 2009-11-17Leadframe-based semiconductor package having arched bend in a supporting bar and leadframe for the package
#54 | 2009-12-10 ✅ Patent 7,622,794 granted on 2009-11-24COL (Chip-On-Lead) multi-chip package
#55 | 2009-12-03Method for Fabricating Semiconductor Elements
#56 | 2009-12-03Lead Frame and Chip Package Structure and Method for Fabricating the Same
#57 | 2009-11-19 ✅ Patent 7,750,444 granted on 2010-07-06Lead-on-chip semiconductor package and leadframe for the package
#58 | 2009-11-12 ✅ Patent 7,902,663 granted on 2011-03-08Semiconductor package having stepwise depression in substrate
#59 | 2009-10-29 ✅ Patent 7,838,967 granted on 2010-11-23Semiconductor chip having TSV (through silicon via) and stacked assembly including the chips
#60 | 2009-10-01 ✅ Patent 7,732,921 granted on 2010-06-08Window type BGA semiconductor package and its substrate
#61 | 2009-09-24 ✅ Patent 7,884,472 granted on 2011-02-08Semiconductor package having substrate ID code and its fabricating method
#62 | 2009-09-10 ✅ Patent 7,692,313 granted on 2010-04-06Substrate and semiconductor package for lessening warpage
#63 | 2009-09-10 ✅ Patent 7,952,168 granted on 2011-05-31Substrate strip for semiconductor packages
#64 | 2009-09-10 ✅ Patent 7,812,430 granted on 2010-10-12Leadframe and semiconductor package having downset baffle paddles
#65 | 2009-09-10 ✅ Patent 7,821,112 granted on 2010-10-26Semiconductor device with wire-bonding on multi-zigzag fingers
#66 | 2009-08-13Electronic packaging method and apparatus
#67 | 2009-08-04 ✅ Patent 7,569,935 granted on 2009-08-04Pillar-to-pillar flip-chip assembly
#68 | 2009-07-21 ✅ Patent 7,564,123 granted on 2009-07-21Semiconductor package with fastened leads
#69 | 2009-07-09 ✅ Patent 7,605,018 granted on 2009-10-20Method for forming a die-attach layer during semiconductor packaging processes
#70 | 2009-07-09 ✅ Patent 7,919,715 granted on 2011-04-05Circuit board ready to slot
#71 | 2009-06-25 ✅ Patent 7,723,828 granted on 2010-05-25Semiconductor package with leads on a chip having multi-row of bonding pads
#72 | 2009-06-23 ✅ Patent 7,549,568 granted on 2009-06-23Method of forming identification code for wire-bonding machines
#73 | 2009-05-21 ✅ Patent 7,696,618 granted on 2010-04-13POP (package-on-package) semiconductor device
#74 | 2009-05-21 ✅ Patent 7,692,311 granted on 2010-04-06POP (package-on-package) device encapsulating soldered joints between external leads
#75 | 2009-05-21 ✅ Patent 7,566,963 granted on 2009-07-28Stacked assembly of semiconductor packages with fastening lead-cut ends of leadframe
#76 | 2009-04-16Semiconductor package and substrate for the same
#77 | 2009-02-19 ✅ Patent 7,619,305 granted on 2009-11-17Semiconductor package-on-package (POP) device avoiding crack at solder joints of micro contacts during package stacking
#78 | 2008-10-30 ✅ Patent 7,663,204 granted on 2010-02-16Substrate for multi-chip stacking, multi-chip stack package utilizing the substrate and its applications
#79 | 2008-06-26 ✅ Patent 7,408,245 granted on 2008-08-05IC package encapsulating a chip under asymmetric single-side leads
#80 | 2008-06-19 ✅ Patent 7,547,974 granted on 2009-06-16Wiring substrate with improvement in tensile strength of traces
#81 | 2008-04-24 ✅ Patent 7,432,601 granted on 2008-10-07Semiconductor package and fabrication process thereof
#82 | 2008-03-06 ✅ Patent 7,675,186 granted on 2010-03-09IC package with a protective encapsulant and a stiffening encapsulant
#83 | 2008-02-21CHIP PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
#84 | 2007-12-27CIRCUIT SUBSTRATE WITH STRONG ADHESION
#85 | 2007-12-06Ball grind array package structure
Also check out Powertech Technology Inc.'s (Hsinchu, Taiwan) applicant profile with 17 patent applications submitted.
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