209302 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by; Applying interconnections to be used for carrying current between separate components within a device; Formation and after-treatment of dielectrics; Forming openings in dielectrics for dual damascene structures Pre-forming the dual damascene structure in a resist layer
Semiconductor Device and Method of Forming an Embedded Redistribution Layer
#2SELECTIVE RECESSING TO FORM A FULLY ALIGNED VIA
#3Selective recessing to form a fully aligned via
#4Method for fabricating semiconductor device with contact structure
#5Semiconductor Device and Method of Forming an Embedded Redistribution Layer
#6Selective recessing to form a fully aligned via
#7Selective recessing to form a fully aligned via
#8Methods of forming interconnect structures using via holes filled with dielectric film
#9Method of forming semiconductor structure
#10Selective recessing to form a fully aligned via
#11Selective recessing to form a fully aligned via
#12Selective recessing to form a fully aligned via
#13Method of fabricating dual damascene structure
#14Semiconductor devices and methods of manufacture thereof
#15Method of semiconductor integrated circuit fabrication
#16DUAL DAMASCENE PROCESS AND APPARATUS
#17Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme
#18Process of multiple exposures with spin castable films
#19Method of fabricating damascene structures
#20Dual damascene copper process using a selected mask
#21Pattern formation method
#22Method of fabricating dual damascene structures using a multilevel multiple exposure patterning scheme
#23Nano imprint technique with increased flexibility with respect to alignment and feature shaping
#24THREE-STATE MASK AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
#25METHODS AND APPARATUS FOR FORMING LINE AND PILLAR STRUCTURES FOR THREE DIMENSIONAL MEMORY ARRAYS USING A DOUBLE SUBTRACTIVE PROCESS AND IMPRINT LITHOGRAPHY
#26Methods and apparatus for forming memory lines and vias in three dimensional memory arrays using dual damascene process and imprint lithography
#27Process of multiple exposures with spin castable film
#28Method for fabricating dual damascene profiles using sub pixel-voting lithography and devices made by same
#29Dual damascence copper process using a selected mask
#30Nano imprint technique with increased flexibility with respect to alignment and feature shaping
#31Fabrication method
#32Single mask process for variable thickness dual damascene structures, other grey-masking processes, and structures made using grey-masking
#33Method of forming metal wiring in semiconductor device
#34Method for forming dual damascene pattern in semiconductor manufacturing process
#35SINGLE MASK PROCESS FOR VARIABLE THICKNESS DUAL DAMASCENE STRUCTURES, OTHER GREY-MASKING PROCESSES, AND STRUCTURES MADE USING GREY-MASKING
#36Method of forming metal line in semiconductor device
#37Method for forming interconnection line in semiconductor device using a phase-shift photo mask
#38Via patterning using multiple photo multiple etch