209303 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by; Applying interconnections to be used for carrying current between separate components within a device; Formation and after-treatment of dielectrics; Forming openings in dielectrics for dual damascene structures the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
#2SEMICONDUCTOR STRUCTURE
#3SEMICONDUCTOR DEVICE WITH SPACERS FOR SELF ALIGNED VIAS
#4Semiconductor structure and method for forming the same
#5Semiconductor device with spacers for self aligned vias
#6Etch damage and ESL free dual damascene metal interconnect
#7Method for fabricating semiconductor device
#8INTERCONNECTION STRUCTURE WITH SIDEWALL PROTECTION LAYER
#9Semiconductor device with spacers for self aligned vias
#10Fully self-aligned via
#11Chip package
#12Self-aligned contact and contact over active gate structures
#13Method for fabricating semiconductor device
#14Multifunction single via patterning
#15Multifunction single via patterning
#16Vias and gaps in semiconductor interconnects
#17CHIP package
#18Method For Increasing The Verticality Of Pillars
#19Etch damage and ESL free dual damascene metal interconnect
#20Methods of producing self-aligned vias
#21Methods of producing self-aligned grown via
#22Methods of producing self-aligned vias
#23Curtain airbag device mounting structure and curtain airbag deployment method
#24Method of forming interconnection structure
#25Semiconductor device manufacturing method
#26Manufacturing methods to protect ULK materials from damage during etch processing to obtain desired features
#27Etch damage and ESL free dual damascene metal interconnect
#28Method of forming trenches with different depths
#29Integrated fan-out package and method for fabricating the same
#30Method of forming trenches with different depths
#31SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES
#32Multi-layer structure for high aspect ratio etch
#33Etch damage and ESL free dual damascene metal interconnect
#34Metallization method for semiconductor structures
#35Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer
#36Etch damage and ESL free dual damascene metal interconnect
#37Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication
#38Self-aligned fine pitch permanent on-chip interconnect structures and method of fabrication
#39CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FORM DIELECTRIC LAYER
#40Method for forming a dual damascene structure
#41METHOD FOR FORMING SEMICONDUCTOR DEVICE
#42Multilayer interconnect structure containing air gaps and method for making
#43METHOD FOR FORMING FEATURE DEFINITIONS
#44Process for producing semiconductor integrated circuit device
#45Self-patterning of photo-active dielectric materials for interconnect isolation
#46Method of manufacturing a semiconductor device and semiconductor obtained by means of such a method
#47Dual damascene trench formation to avoid low-K dielectric damage
#48Self-patterning of photo-active dielectric materials for interconnect isolation
#49Method for producing an electrically conductive contact
#50Multifunction single via patterning