209304 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by; Applying interconnections to be used for carrying current between separate components within a device; Formation and after-treatment of dielectrics; Forming openings in dielectrics for dual damascene structures Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
INTERCONNECT STRUCTURE AND METHODS THEREOF
#2Semiconductor arrangement and method of making
#3INTERCONNECT STRUCTURE AND METHODS THEREOF
#4Semiconductor arrangement and method of making
#5Etch damage and ESL free dual damascene metal interconnect
#6INTERCONNECTION STRUCTURE WITH SIDEWALL PROTECTION LAYER
#7Semiconductor arrangement and method of making
#8Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
#9Devices including conductive interconnect structures, related electronic systems, and related methods
#10Interconnect structure and method of forming the same
#11Etch damage and ESL free dual damascene metal interconnect
#12Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
#13Conductive line system and process
#14Selectively etched self-aligned via processes
#15Semiconductor devices
#16In-line protection from process induced dielectric damage
#17Dual-damascene formation with dielectric spacer and thin liner
#18Semiconductor devices
#19Interconnect structure and methods thereof
#20Fin-like field effect transistor device
#21Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
#22Interconnect structure and method of forming the same
#23Method for manufacturing interconnection
#24Via blocking layer
#25Fabrication method of semiconductor substrate
#26Memory device and operation method thereof
#27Method of forming interconnection structure
#28Conductive line system and process
#29Semiconductor device manufacturing method
#30Etch damage and ESL free dual damascene metal interconnect
#31Via blocking layer
#32Semiconductor constructions
#33Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components
#34Integrated circuit with a sidewall layer and an ultra-thick metal layer and method of making
#35Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
#36Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
#37Conductive line system and process
#38Semiconductor device and method for manufacturing the same
#39Etch damage and ESL free dual damascene metal interconnect
#40Semiconductor constructions
#41Air-gap assisted etch self-aligned dual Damascene
#42Conductive line system and process
#43Semiconductor substrate and fabrication method thereof
#44Integrated circuit with a sidewall layer and an ultra-thick metal layer and method of making
#45Semiconductor device including passivation layer encapsulant
#46Methods for fabrication of an air gap-containing interconnect structure
#47Interconnect structure and method
#48Etch damage and ESL free dual damascene metal interconnect
#49Interconnect structure and method of fabricating
#50Semiconductor device, fabrication method for a semiconductor device and electronic apparatus
#51INTERCONNECT STRUCTURE FABRICATED WITHOUT DRY PLASMA ETCH PROCESSING
#52Self-aligned permanent on-chip interconnect structures
#53Interconnect structures containing a photo-patternable low-k dielectric with a curved sidewall surface
#54Interconnect structure including a modified photoresist as a permanent interconnect dielectric and method of fabricating same
#55Gap filling method for dual damascene process
#56Methodology for evaluation of electrical characteristics of carbon nanotubes
#57Air gap-containing interconnect structure having photo-patternable low k material
#58Interconnect structure and method for fabricating on-chip interconnect structures by image reversal
#59Patternable low-K dielectric interconnect structure with a graded cap layer and method of fabrication
#60Self-aligned dual damascene BEOL structures with patternable low-k material and methods of forming same
#61Self-aligned permanent on-chip interconnect structure formed by pitch splitting
#62Method for forming semiconductor device
#63Methods of forming semiconductor devices
#64Self-aligned permanent on-chip interconnect structure formed by pitch splitting
#65Methods to form self-aligned permanent on-chip interconnect structures
#66Semiconductor device and method for forming the same
#67Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction
#68Patternable dielectric film structure with improved lithography and method of fabricating same
#69Methodology for evaluation of electrical characteristics of carbon nanotubes
#70Interconnect structure and method of fabricating
#71Method for air gap interconnect integration using photo-patternable low k material
#72Methods for fabrication of an air gap-containing interconnect structure
#73Methods for photo-patternable low-k (PPLK) integration with curing after pattern transfer
#74Interconnect structure including a modified photoresist as a permanent interconnect dielectric and method of fabricating same
#75Photo-patternable dielectric materials curable to porous dielectric materials, formulations, precursors and methods of use thereof
#76Patternable low-k dielectric interconnect structure with a graded cap layer and method of fabrication
#77Airgap-containing interconnect structure with improved patternable low-K material and method of fabricating
#78Interconnect structure fabricated without dry plasma etch processing
#79Self-aligned dual damascene BEOL structures with patternable low- K material and methods of forming same
#80Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material
#81MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH AIR GAPS FORMED COMMONLY WITH VIAS
#82Method of forming an interconnect structure
#83Method of making an interconnect structure
#84Artificially tilted via connection
#85Dielectric materials and methods for integrated circuit applications
#86Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics
#87Patternable dielectric film structure with improved lithography and method of fabricating same
#88CONDUCTIVE ELEMENT FORMING USING SACRIFICIAL LAYER PATTERNED TO FORM DIELECTRIC LAYER
#89Method for manufacturing a semiconductor device and method for etching the same
#90Dual damascene with via liner
#91Semiconductor device and method of manufacturing thereof
#92Method of formation of a damascene structure utilizing a protective film
#93Multilayer interconnect structure containing air gaps and method for making
#94SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD
#95Semiconductor device with a capacitor
#96Poly(organosiloxane) materials and methods for hybrid organic-inorganic dielectrics for integrated circuit applications
#97Semiconductor device and method of manufacturing thereof
#98Method for manufacturing a semiconductor device and method for etching the same
#99Dual damascene with via liner
#100Method of manufacturing a semiconductor device and semiconductor device obtained by using such a method
#101Materials and methods for forming hybrid organic-inorganic dielectric materials for integrated circuit applications
#102Thin films and methods for the preparation thereof
#103Method for forming an interconnection line in a semiconductor device
#104Dual damascene trench formation to avoid low-K dielectric damage
#105Method of depositing low k films
#106Wiring structure of a semiconductor integrated circuit and a method of forming the wiring structure
#107Method of manufacturing a semiconductor device having damascene structures with air gaps
#108Plasma processes for depositing low dielectric constant films
#109Method for manufacturing semiconductor device using dual-damascene pattern
#110METHOD OF PATTERNING LOW-K FILM AND METHOD OF FABRICATING DUAL-DAMASCENE STRUCTURE
#111Semiconductor device and manufacturing method of the same
#112Dielectric materials and methods for integrated circuit applications