209305 ⎘
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by; Applying interconnections to be used for carrying current between separate components within a device; Formation and after-treatment of dielectrics; Forming openings in dielectrics for dual damascene structures Dual damascene with different via-level and trench-level dielectrics
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
#2METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH DAMASCENE STRUCTURE BY USING ETCH STOP LAYER
#3SEMICONDUCTOR STRUCTURE
#4SELF-ASSEMBLED GUIDED HOLE AND VIA PATTERNING OVER GRATING
#5SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME
#6INTEGRATED CIRCUIT DEVICE INCLUDING INTERCONNECTION STRUCTURE
#7Semiconductor device structure and method for preparing the same
#8Method for fabricating semiconductor device with damascene structure by using etch stop layer
#9Method for fabricating semiconductor device with damascene structure
#10REPLACEMENT CONDUCTIVE MATERIAL FOR INTERCONNECT FEATURES
#11Semiconductor structure and method for forming the same
#12Etch damage and ESL free dual damascene metal interconnect
#13Method for preparing semiconductor device structure with fine patterns at different levels
#14Semiconductor device and method of manufacturing semiconductor device
#15Semiconductor structure and fabrication method thereof
#16Semiconductor device structure with fine patterns at different levels and method for forming the same
#17Fully self-aligned via
#18Hybrid dielectric scheme for varying liner thickness and manganese concentration
#19Semiconductor device and method of manufacturing semiconductor device
#20Etch damage and ESL free dual damascene metal interconnect
#21Semiconductor interconnect structure having a graphene barrier layer
#22Self-formed liner for interconnect structures
#23Selectively etched self-aligned via processes
#24Advanced BEOL interconnect architecture
#25Hybrid dielectric scheme for varying liner thickness and manganese concentration
#26Integrating metal-insulator-metal capacitors with air gap process flow
#27Semiconductor interconnect structure having a graphene barrier layer
#28Self-formed liner for interconnect structures
#29Semiconductor device manufacturing method
#30Etch damage and ESL free dual damascene metal interconnect
#31Integrating metal-insulator-metal capacitors with air gap process flow
#32SELF-ALIGNED DEVICE LEVEL CONTACT STRUCTURES
#33Method for bonding and interconnecting integrated circuit devices
#34Etch damage and ESL free dual damascene metal interconnect
#35Vertical breakdown protection layer
#36Aluminum interconnection apparatus
#37Method for forming wiring
#38Interconnect structure and method of forming the same
#39Semiconductor device manufacturing method, and photoelectric conversion device
#40ADVANCED INTERCONNECT WITH AIR GAP
#41Aluminum interconnection apparatus
#42Dual-damascene process to fabricate thick wire structure
#43Semiconductor device and method for manufacturing semiconductor device
#44Etch damage and ESL free dual damascene metal interconnect
#45Aluminum interconnection apparatus
#46Semiconductor device and method of manufacturing the same
#47Etch damage and ESL free dual damascene metal interconnect
#48Single exposure in multi-damascene process
#49Air gap-containing interconnect structure having photo-patternable low k material
#50INTERCONNECT STRUCTURE HAVING A VIA WITH A VIA GOUGING FEATURE AND DIELECTRIC LINER SIDEWALLS FOR BEOL INTEGRATION
#51Dual-damascene process to fabricate thick wire structure
#52Method to reduce depth delta between dense and wide features in dual damascene structures
#53STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES
#54Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction
#55Method for air gap interconnect integration using photo-patternable low k material
#56Self-aligned barrier layers for interconnects
#57METHOD AND STRUCTURE FOR ELECTRO-PLATING ALUMINUM SPECIES FOR TOP METAL FORMATION OF LIQUID CRYSTAL ON SILICON DISPLAYS
#58SEMICONDUCTOR DEVICE
#59Interconnect structure having a via with a via gouging feature and dielectric liner sidewalls for BEOL integration
#60Semiconductor device
#61Method for manufacturing semiconductor device having porous low dielectric constant layer formed for insulation between metal lines
#62Airgap-containing interconnect structure with improved patternable low-K material and method of fabricating
#63Method of aftertreatment of amorphous hydrocarbon film and method for manufacturing electronic device by using the aftertreatment method
#64Microstructure device including a metallization structure with self-aligned air gaps formed based on a sacrificial material
#65Semiconductor device, method of manufacturing the same, and phase shift mask
#66Pseudo hybrid structure for low K interconnect integration
#67Method for forming porous insulating film and semiconductor device
#68Semiconductor device and method for manufacturing same
#69Structures and methods for improving solder bump connections in semiconductor devices
#70Dual-damascene process to fabricate thick wire structure
#71Manufacturing method for semiconductor integrated circuit device
#72Semiconductor device and method for manufacturing semiconductor device
#73Method of manufacturing a device with a cavity
#74Self-aligned barrier layers for interconnects
#75Method for manufacturing semiconductor device
#76Semiconductor device, method of manufacturing the same, and phase shift mask
#77METHOD FOR FORMING AN AIR GAP IN MULTILEVEL INTERCONNECT STRUCTURE
#78Method for manufacturing semiconductor device having porous low dielectric constant layer formed for insulation between metal lines
#79Post last wiring level inductor using patterned plate process
#80Post last wiring level inductor using patterned plate process
#81Post last wiring level inductor using patterned plate process
#82Post last wiring level inductor using patterned plate process
#83Post last wiring level inductor using patterned plate process
#84Method for fabrication of semiconductor device
#85Semiconductor device and method of manufacturing thereof
#86UV CURING OF PECVD-DEPOSITED SACRIFICIAL POLYMER FILMS FOR AIR-GAP ILD
#87Laminated body and semiconductor device
#88Dual-damascene process to fabricate thick wire structure
#89Post last wiring level inductor using patterned plate process
#90Semiconductor device having multilayer wiring lines and manufacturing method thereof
#91Semiconductor device and method of manufacturing thereof
#92Method of manufacturing a semiconductor wafer device having separated conductive patterns in peripheral area
#93Semiconductor device, method of manufacturing the same, and phase shift mask
#94Bilayered metal hardmasks for use in dual damascene etch schemes
#95Semiconductor device
#96Semiconductor device
#97Semiconductor wafer device having separated conductive patterns in peripheral area and its manufacture method
#98Semiconductor apparatus
#99Method to generate porous organic dielectric
#100Semiconductor device
#101Semiconductor device manufactured by the damascene process having improved stress migration resistance
#102Insulating layer having graded densification
#103Semiconductor device and method for manufacturing the same
#104Semiconductor device with dual damascene wiring
#105Self-assembled guided hole and via patterning over grating
#106Interconnect formation process using wire trench etch prior to via etch, and related interconnect
#107Contact scheme for landing on different contact area levels