SEMICONDUCTOR DEVICE HAVING NON-CIRCULAR CONNECTORS

Devices, packaging devices, and methods of packaging semiconductor devices

Bonding package components through plating

Semiconductor device and method of adaptive patterning for panelized packaging with dynamic via clipping

Device electrode formation using metal sheet

Semiconductor device and a method of manufacturing the same

3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach

Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components

Methods of packaging semiconductor devices and structures thereof

Conductive line system and process

Testing of semiconductor chips with microbumps

Package-on-package semiconductor device

Method of manufacturing a chip package

Semiconductor device

Flip chip assembly and process with sintering material on metal bumps

Bump structure and method of forming same

Semiconductor device and manufacturing method therefor

Semiconductor device

Packaged semiconductor devices and packaging devices and methods

Integrated electronic package and method of fabrication

Through via structure

3D packages and methods for forming the same

Three-dimensional semiconductor architecture

Method of making integrated circuit

Method for producing an electronic assembly

Radiation hardened by design digital input/output circuits and related methods

Shielded package assemblies with integrated capacitor

Process for forming package-on-package structures

Package on-package with cavity in interposer

Semiconductor device

Structure and method for integrated circuits packaging with increased density

Plurality of semiconductor devices in resin with a via

Method of forming a semiconductor component comprising a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer

Circuit module and method of manufacturing the same

Adjusting sizes of connectors of package components

Methods of fabricating semiconductor chip solder structures

3D IC method and device

Fabrication method of package having ESD and EMI preventing functions

Electrostatic discharge diodes and methods of forming electrostatic discharge diodes

Stacked microelectronic assembly with TSVs formed in stages with plural active chips

Articles including bonded metal structures and methods of preparing the same

Method of forming solder bump, and solder bump

Semiconductor device having solderable and bondable electrical contact pads

Contact pads for integrated circuit packages

Semiconductor structure with composite barrier layer under redistribution layer and manufacturing method thereof

Metal pad offset for multi-layer metal layout

Semiconductor device and production method therefor

Semiconductor devices and methods of fabricating the same

Chip package and method for forming the same

Metal bump joint structure

Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same

Chip packaging structures and treatment methods thereof

Semiconductor device

Method of forming post-passivation interconnect structure

INTEGRATED CIRCUIT

Methods and apparatus of guard rings for wafer-level-packaging

Photosensitive resin composition, method for producing patterned cured film, semiconductor element and electronic device

Devices and systems comprising drivers for power conversion circuits

Stacked dies with wire bonds and method

Method of fabricating semiconductor package, semiconductor package formed thereby, and semiconductor device including the same

Bump structure having a side recess and semiconductor structure including the same

Semiconductor package and method of manufacturing the same

Metal cored solder decal structure and process

Bonding structures and methods of forming the same

Semiconductor chip having different conductive pad widths and method of making layout for same

Semiconductor device having low dielectric insulating film and manufacturing method of the same

Methods of fabrication and testing of three-dimensional stacked integrated circuit system-in-package

Wafer, package structure and method of manufacturing the same

Integrated circuit system with debonding adhesive and method of manufacture thereof

Electronic component and electronic device

Polymer layers embedded with metal pads for heat dissipation

Electromagnetic bandgap structure for three dimensional ICS

Semiconductor device

SCRIBE LINE STRUCTURE AND METHOD OF FORMING SAME

Method of forming chip with through silicon via electrode

Tin plating solution, tin plating equipment, and method for fabricating semiconductor device using the tin plating solution

Connector structures of integrated circuits

Metal contact for semiconductor device

Bowl-shaped solder structure

Power management applications of interconnect substrates

Composite compositions for electronics applications

Dicing wafers having solder bumps on wafer backside

Semiconductor with through-substrate interconnect

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Optoelectronic component with integrated protection diode and method of producing same

3D integrated circuit package with through-mold first level interconnects

Integrated electronic device with transceiving antenna and magnetic interconnection

Interconnection structure having a via structure and fabrication thereof

Circuits incorporating integrated passive devices having inductances in 3D configurations and stacked with corresponding dies

Hybrid on-chip and package antenna

Method for making a sensor device using a graphene layer

Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP

Packages with metal line crack prevention design

Semiconductor device including a buffer layer structure for reducing stress

Integrated circuit chip and fabrication method

Metal contact for semiconductor device

Solder pad for semiconductor device package

Semiconductor sensor device and method of producing a semiconductor sensor device

Through-silicon via with low-K dielectric liner

Collapsible probe tower device and method of forming thereof

Semiconductor devices having hybrid stacking structures and methods of fabricating the same

Semiconductor device

Recessed semiconductor substrates and associated techniques

LPS solder paste based low cost fine pitch pop interconnect solutions

Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment

Wafer level device and method with cantilever pillar structure

Manufacture of coated copper pillars

Metal pillar bump packaging strctures and fabrication methods thereof

Semiconductor chip with patterned underbump metallization and polymer film

Drive chip and display apparatus

Semiconductor device with thick bottom metal and preparation method thereof

Semiconductor device, imaging device and semiconductor device manufacturing method

Semiconductor package with via-coupled power transistors

Semiconductor packages and methods of forming the same

Semiconductor device having semiconductor chips in resin and electronic circuit device with the semiconductor device

Semiconductor device package and method of the same

Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package

Chip package and method thereof

Semiconductor packages and methods of forming the same

Metal electromagnetic interference (EMI) shielding coating along an edge of a ceramic substrate

Semiconductor devices including through-silicon via

Semiconductor device and manufacturing method thereof

Integrated circuit assemblies with reinforcement frames, and methods of manufacture

3D packages and methods for forming the same

Semiconductor device structure and manufacturing method

Solder stud structure

Semiconductor device structure and manufacturing method

Bump structure and method for forming the same

Methods and apparatus of packaging semiconductor devices

COF type semiconductor package and method of manufacturing the same

Semiconductor device having fan-in and fan-out redistribution layers

Integrated circuit package

Method for manufacturing semiconductor device and semiconductor device

Package structure and manufacturing method

Methods for controlling warpage in packaging

Method of manufacturing a semiconductor device including removing a relief layer from back surface of semiconductor chip

Semiconductor packages and data storage devices including the same

Semiconductor device and method of forming microelectromechanical systems (MEMS) package

Methods of forming III-V semiconductor structures using multiple substrates, and semiconductor devices fabricated using such methods

3-D inductor and transformer

Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device

Interconnect structure for package-on-package devices and a method of fabricating

Single mask package apparatus

Solution for reducing poor contact in info packages

Semiconductor package and method

Package-on-package assembly with wire bond vias

Semiconductor device and manufacturing method thereof

Enhanced board level reliability for wafer level packages

Embedded die flip-chip package assembly

Mechanically anchored backside C4 pad

Solder ball protection in packages

Electrical connectivity of die to a host substrate

Semiconductor device and method of manufacturing same

Semiconductor device

Package on package structure and fabrication method thereof

Chip package having extended depression for electrical connection and method of manufacturing the same

Low-stress dual underfill packaging

Method of fabricating semiconductor package

Method of forming package assembly

Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers

Enhanced flip chip structure using copper column interconnect

Chip diode and diode package

Thin NiB or CoB capping layer for non-noble metallic bonding landing pads

Backside integration of RF filters for RF front end modules and design structure

Electrode provided with UBM structure having a barrier layer for reducing solder diffusion into the electrode and a method for producing the same

Packages and methods for forming the same

Integrated circuit package

Integrated passive flip chip package

Laser marking in packages

Multiple die in a face down package

Microelectronic packages with nanoparticle joining

Package structure and method of forming the same

Substrate and package structure

Packages with solder ball revealed through laser

Packaging devices and methods

Packaging devices and methods of manufacture thereof

Method for manufacturing semiconductor device

Semiconductor chip and semiconductor chip package each having signal paths that balance clock skews

Semiconductor device

Method of forming surface protrusions on an article and the article with the protrusions attached

Solder paste, joining method using the same and joined structure

Semiconductor device having wires connecting connection pads

Thermal performance structure for semiconductor packages and method of forming same

Bottom package with metal post interconnections

Substrate design for semiconductor packages and method of forming same

Substrate design for semiconductor packages and method of forming same

Semiconductor device and semiconductor device manufacturing method

Flow diversion devices

Protection circuit including vertical gallium nitride schottky diode and PN junction diode

Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation

Semiconductor device and method of manufacturing the same

Self-aligning conductive bump structure and method of fabrication

Packages with stress-reducing structures and methods of forming same

Self-alignment structure for wafer level chip scale package

Semiconductor device with post-passivation interconnect structure and method of forming the same

Copper post structure for wafer level chip scale package

Semiconductor packaging structure and manufacturing method for the same

Semiconductor device

Semiconductor device and method of manufacturing the same

Methods of making integrated circuits including conductive structures through substrates

Bonded processed semiconductor structures and carriers

Method of forming Cu pillar bump with non-metal sidewall spacer and metal top cap

Metal-insulator-metal (MIM) capacitor in redistribution layer (RDL) of an integrated device

Semiconductor device and method of manufacturing the same

Semiconductor device and connection checking method for semiconductor device

Thermal pads between stacked semiconductor dies and associated systems and methods

Methods of packaging semiconductor devices and packaged semiconductor devices

Semiconductor device and manufacturing method thereof

Semiconductor device

Microbump and sacrificial pad pattern

Flip-chip hybridisation of two microelectronic components using a UV anneal

Semiconductor device with redistribution layers formed utilizing dummy substrates

Semiconductor device and manufacturing method thereof

Semiconductor device manufacturing method and semiconductor mounting substrate

Multi-dimensional integrated circuit structures and methods of forming the same

Microelectronic assembly having a heat spreader for a plurality of die

Stacked semiconductor system having interposer of half-etched and molded sheet metal

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Methods for forming a semiconductor device package

Chip mounting structure and manufacturing method therefor

Semiconductor module

Package substrate structure for enhanced signal transmission and method

Method of fabricating connection structure for a substrate

Substrate structure and fabrication method thereof

System and method for 3D integrated circuit stacking

Bonding pad structure with dense via array

Passive component structure and manufacturing method thereof

Packages for three-dimensional die stacks

Inductor for post passivation interconnect and a method of forming

System and method for bonding package lid

Methods for processing substrates

Assembly bonding

Anisotropic conductive adhesive

Contact bump connection and contact bump and method for producing a contact bump connection

Test structure and method of testing electrical characteristics of through vias

Semiconductor apparatus capable of detecting whether pad and bump are stacked

Integrated circuit package and methods of forming same

Flip-chip package structure and method for an integrated switching power supply

GaN transistor with improved bonding pad structure and method of fabricating the same

Interconnect structure and method of forming same

Semiconductor device with through silicon via and alignment mark

I/O pin capacitance reduction using TSVS

Chip package and method of manufacturing the same

Method of manufacturing semiconductor device

Substrate composite, method and device for bonding of substrates

Pad structure design in fan-out package

WAFER LEVEL PACKAGE WITH REDISTRIBUTION LAYER FORMED WITH METALLIC POWDER

Semiconductor device

Semiconductor structure and manufacturing method thereof

Packaging through pre-formed metal pins

Semiconductor device

Semiconductor device having a switch that expands and contracts by temperature change

Stacked semiconductor package

Stub minimization for multi-die wirebond assemblies with parallel windows

Semiconductor assemblies, stacked semiconductor devices, and methods of manufacturing semiconductor assemblies and stacked semiconductor devices

Stud bump and package structure thereof and method of manufacturing the same

Protrusion bump pads for bond-on-trace processing

Semiconductor package

Method of fabricating bump structure and bump structure

Barrier structures between external electrical connectors

Method of fabricating a bond pad structure

Semiconductor integrated circuit device having protective split at peripheral area of bonding pad and method of manufacturing same

Power overlay structure and method of making same

Structure and method for 3D IC package

Semiconductor package, fabrication method therefor, and package-on package

Chip stack with electrically insulating walls

Molding package assembly and molding material

Method and apparatus for a conductive pillar structure

Package on package bonding structure and method for forming the same

Semiconductor package and fabrication method thereof

Semiconductor device

Semiconductive packaging device and manufacturing method thereof

Reduced stress TSV and interposer structures

Through via contacts with insulated substrate

Three dimensional integrated circuit (3DIC) having a thermally enhanced heat spreader embedded in a substrate

Semiconductor device and method of forming build-up interconnect structures over a temporary substrate

Semiconductor device and method of manufacturing semiconductor device

Method for aligning micro-electronic components

Grid array connection device and method

Solder-on-die using water-soluble resist system and method

Low z-height package assembly

Self-aligned under bump metal

Substrate comprising improved via pad placement in bump area

Semiconductor device and method of forming stress relief layer between die and interconnect structure

Semiconductor device with advanced pad structure resistant to plasma damage and method for forming the same

Methods and apparatus for package with interposers

Forming functionalized carrier structures with coreless packages

Semiconductor device

Three-dimensional integrated circuit structures providing thermoelectric cooling and methods for cooling such integrated circuit structures

Methods and apparatus for wafer level packaging

Method of manufacturing printed circuit board and printed circuit board

Insulated gate semiconductor device and method

Thermally enhanced wafer level fan-out POP package

BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility

Bump structures for semiconductor package

Formation of connectors without UBM

Component-embedded board and communication terminal device

Chip, chip package and die

Packaged semiconductor devices and methods of packaging semiconductor devices

Interconnect structures with polymer core