Electronic apparatus and method for fabricating the same

Multiple active vertically aligned cores for three-dimensional chip stack

Interposer-chip-arrangement for dense packaging of chips

Method of forming a semiconductor device and structure therefor

Methods of forming semiconductor die assemblies

Intermetallic compound layer on a pillar between a chip and substrate

Method for handling very thin device wafers

Protective layer for contact pads in fan-out interconnect structure and method of forming same

Semiconductor device

Stacked three dimensional semiconductor device with in-circuit antenna

Intelligent chip placement within a three-dimensional chip stack

Method and structure for wafer level packaging with large contact area

Intelligent chip placement within a three-dimensional chip stack

Package structure and methods of forming same

Tunable composite interposer

Multiple active vertically aligned cores for three-dimensional chip stack

Microelectronic structures having laminated or embedded glass routing structures for high density packaging

Device including two power semiconductor chips and manufacturing thereof

Multiple die stacking for two or more die

Semiconductor package

Semiconductor packages including a multi-layered dielectric layer and methods of manufacturing the same

Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package

Carrier-less silicon interposer using photo patterned polymer as substrate

SEMICONDUCTOR CHIP AND METHOD OF FORMING THE SAME

Method for generating die identification by measuring whether circuit is established in a package structure

TSV substrate structure and the stacked assembly thereof

Packages with molding material forming steps

Substrates having ball lands, semiconductor packages including the same, and methods of fabricating semiconductor packages including the same

Semiconductor packaging and manufacturing method thereof

Mechanisms for forming package structure

Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die

Semiconductor package

Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP

Integrated circuits with internal pads

Thin embedded packages, methods of fabricating the same, electronic systems including the same, and memory cards including the same

Integrated circuit and fabricating method thereof

Chip package and method for forming the same

Discrete semiconductor device package and manufacturing method

Wafer level semiconductor package and manufacturing methods thereof

Vertical conductive connections in semiconductor substrates

Self-alignment for redistribution layer

Semiconductor device assembly with package interconnect extending into overlying spacer material, and associated systems, devices, and methods

Stacked microelectronic devices

Through silicon via structure

TSV structures and methods for forming the same

Semiconductor device and manufacturing method thereof

Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods

Mechanisms for forming post-passivation interconnect structure

Semiconductor device and fabricating method thereof

Semiconductor device and manufacturing method thereof

Stacked semiconductor package and manufacturing method thereof

Semiconductor assembly and method of manufacturing the same

Pattern generator having stacked chips

Fabrication methods of chip device packages

Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same

Package on-Package (PoP) structure including stud bulbs and method

PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Configurable routing for packaging applications

Semiconductor element

Staged via formation from both sides of chip

Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure

Post passivation interconnect structures and methods for forming the same

Semiconductor device and method of manufacturing semiconductor device

Chip-on-wafer structures and methods for forming the same

Semiconductor device including semiconductor chips stacked via relay substrate

Semiconductor packaging device including via-in pad (VIP) and manufacturing method thereof

Semiconductor package with package-on-package stacking capability and method of manufacturing the same

Semiconductor package and method of fabricating the same

Semiconductor packaging and manufacturing method thereof

Thermal dissipation through seal rings in 3DIC structure

Apparatus and method of attaching solder ball and method of fabricating semiconductor package including solder ball

Method of forming interconnection structure of package structure

Die-to-die gap control for semiconductor structure and method

Semiconductor circuit device, electronic device, electronic apparatus, and moving object

Chip device packages and fabrication methods thereof

Methods and apparatus of packaging semiconductor devices

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

Thermocompression for semiconductor chip assembly

Packaging devices and methods of manufacture thereof

Semiconductor devices and methods of forming thereof

Semiconductor device and method for manufacturing the same

Alignment marks in substrate having through-substrate via (TSV)

Semiconductor integrated circuit device

Flip-chip, face-up and face-down centerbond memory wirebond assemblies

Semiconductor package having magnetic connection member

Chip on package structure and method

Wafer arrangement, a method for testing a wafer, and a method for processing a wafer

Semiconductor structure and manufacturing method thereof

Semiconductor device for use in flip-chip bonding, which reduces lateral displacement

Stacked semiconductor package including a smaller-area semiconductor chip

Embedded heat spreader for package with multiple microelectronic elements and face-down connection

Semiconductor structure

Methods of stress balancing in gallium arsenide wafer processing

Semiconductor chips having through silicon vias and related fabrication methods and semiconductor packages

Method of manufacturing semiconductor device

Semiconductor package and method of fabricating the same

3-D package having plurality of substrates

Stacked die package with aligned active and passive through-silicon vias

Structure to prevent solder extrusion

Package on package structure and method of manufacturing the same

Submount, encapsulated semiconductor element, and methods of manufacturing the same

Technique for controlling positions of stacked dies

Semiconductor package and method of fabricating the same

Stress buffer structures in a mounting structure of a semiconductor device

Non-conductive film and non-conductive paste including zinc particles, semiconductor package including the same, and method of manufacturing the semiconductor package

Mechanism for forming patterned metal pad connected to multiple through silicon vias (TSVs)

Semiconductor device with shielding layer in post-passivation interconnect structure

Chip-stacked semiconductor package and method of manufacturing the same

Vertical semiconductor device with thinned substrate

Semiconductor substrate assembly with embedded resistance element

Electrical connections for chip scale packaging

Plug via formation with grid features in the passivation layer

Chip packages, chip arrangements, a circuit board, and methods for manufacturing chip packages

Semiconductor device and method for manufacturing the same

Semiconductor devices having through-vias and methods for fabricating the same

Microelectronic devices with through-substrate interconnects and associated methods of manufacturing

3D device packaging using through-substrate pillars

Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration

Semiconductor device

3D device packaging using through-substrate posts

Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer

Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP

Semiconductor device and electronic unit provided with the same

Semiconductor chip and stacked semiconductor package having the same

Package assembly and methods for forming the same

Connection member, semiconductor device, and stacked structure

Semiconductor device and method of forming dual fan-out semiconductor package

Chip package and method for forming the same

Die edge side connection

Formation of through-silicon via (TSV) in silicon substrate

Semiconductor package and method of fabricating the same

Electronic device, test board, and semiconductor device manufacturing method

Liquid compositions and methods of fabricating a semiconductor device using the same

Electrostatic discharge protection apparatus and process

Semiconductor device having stacked chips

Integrated fan-out package structures with recesses in molding compound

Integrated semiconductor device and wafer level method of fabricating the same

Hollow metal pillar packaging scheme

Semiconductor device assemblies including face-to-face semiconductor dice and related methods

Methods of fabricating wafer-level flip chip device packages

Reducing formation of oxide on solder

Via network structures and method therefor

Bump structures in semiconductor packages and methods of fabricating the same

Method for removing electroplated metal facets and reusing a barrier layer without chemical mechanical polishing

Ablation method and recipe for wafer level underfill material patterning and removal

Methods and apparatus for package on package devices with reversed stud bump through via interconnections

Multiple access over proximity communication

Semiconductor device and fabrication method thereof and semiconductor structure

Copper pillar bump and flip chip package using same

CHIP-ON-FILM DEVICE

Apparatus and method for a component package

Stacked semiconductor package and method for manufacturing the same

Method of room temperature covalent bonding

Optical coupling module

Semiconductor device

ESD protection device

Semiconductor devices and methods of manufacture thereof

Integrated circuit package including in-situ formed cavity

Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation

Semiconductor device and manufacturing method of semiconductor device

Stack packages including diffusion barriers over sidewalls of through via electrodes and methods of manufacturing the same

Three-dimensional chip stack and method of forming the same

Interconnection structure including a metal post encapsulated by solder joint having a concave outer surface

Semiconductor interconnect structure

Electronic device package and fabrication method thereof

Semiconductor packages and methods of packaging semiconductor devices

Substrate, method of fabricating the same, and application the same

Wafer level dicing method

Bottom-up plating of through-substrate vias

Electronic device packages having bumps and methods of manufacturing the same

Substrateless power device packages

Interconnection structure with confinement layer

Semiconductor device and method of forming pad layout for flipchip semiconductor die

Multilayer pillar for reduced stress interconnect and method of making same

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

Stack of semiconductor structures and corresponding manufacturing method

Semiconductor device having stacked substrates with protruding and recessed electrode connection

Semiconductor device with pads of enhanced moisture blocking ability

Inductor structure and manufacturing method thereof

Semiconductor device including asymmetric electrode arrangement

Semiconductor package with embedded die and its methods of fabrication

Chip-on-wafer bonding method and bonding device, and structure comprising chip and wafer

Semiconductor package

Semiconductor devices with through via electrodes, methods of fabricating the same, memory cards including the same, and electronic systems including the same

Crack stopping structure in wafer level packaging (WLP)

SEMICONDUCTOR DEVICE

Multi-chip structure and method of forming same

Alignment structures and methods of forming same

Adhesive for semiconductor, fluxing agent, manufacturing method for semiconductor device, and semiconductor device

Semiconductor package and method of manufacturing the same

Electromagnetic field assisted self-assembly with formation of electrical contacts

Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip

Method for manufacturing a fan-out WLP with package

Method of forming a wire bond having a free end

Packaging methods and structures for semiconductor devices

Embedded packaging with preformed vias

Chip package and fabrication method thereof

3D packages and methods for forming the same

Semiconductor device and method of making wafer level chip scale package

Structures and methods for improving solder bump connections in semiconductor devices

Semiconductor device sealed in a resin section and method for manufacturing the same

Multi-die fine grain integrated voltage regulation

Strength of micro-bump joints

Millimeter wave wafer level chip scale packaging (WLCSP) device and related method

Millimeter wave wafer level chip scale packaging (WLCSP) device

Chip package and fabrication method thereof

Wafer scale package for high power devices

Bump pad structure

Methods for forming conductive elements and vias on substrates and for forming multi-chip modules

Method and apparatus for stacked semiconductor chips

Semiconductor devices with ball strength improvement

Semiconductor devices with close-packed via structures having in-plane routing and method of making same

Semiconductor devices

Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs

Technique for wafer-level processing of QFN packages

Stack packages and methods of fabricating the same

Method of packaging integrated circuits and a molded package

Semiconductor device

On-chip RF shields with backside redistribution lines

Semiconductor device, electronic device, and semiconductor device manufacturing method

Chip to package interface

EMI package and method for making same

Semiconductor package

Front-to-back bonding with through-substrate via (TSV)

Mounting structure and mounting structure manufacturing method

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Semiconductor device

Semiconductor device with redistribution layers on partial encapsulation and non-photosensitive passivation layers

Semiconductor substrate having stress-absorbing surface layer

Semiconductor device and method of forming thermal lid for balancing warpage and thermal management

Semiconductor device with plated pillars and leads

Capacitor in post-passivation structures and methods of forming the same

Method for package-on-package assembly with wire bonds to encapsulation surface

Method of forming a semiconductor package

Dam structure for enhancing joint yield in bonding processes

Embedded structures for package-on-package architecture

Interconnect structure and method of fabricating same

Semiconductor device and fabrication method thereof

Die-on-interposer assembly with dam structure and method of manufacturing the same

Semiconductor device with improved metal pillar configuration

Microelectronic packages having frontside thermal contacts and methods for the fabrication thereof

Semiconductor device having through silicon trench shielding structure surrounding RF circuit

III-Nitride device with solderable front metal

Packaging for high power integrated circuits and infrared emitter arrays

Conductive structure and method for forming the same

Method of forming package systems having interposers

Semiconductor device with pre-molding chip bonding

Semiconductor chip and stacked type semiconductor package having the same

Methods of fluxless micro-piercing of solder balls, and resulting devices

Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionality

Semiconductor chip scale package and manufacturing method thereof

Dummy flip chip bumps for reducing stress

Stacked semiconductor device, printed circuit board, and method for manufacturing stacked semiconductor device

Method of forming molded panel embedded die structure

Die-to-die inductive communication devices and methods

Semiconductor device and method of forming trench and disposing semiconductor die over substrate to control outward flow of underfill material

Semiconductor device and method of stacking semiconductor die on a fan-out WLCSP

Mechanisms for forming hybrid bonding structures with elongated bumps

Semiconductor package

Packaged semiconductor device

Radio frequency shielding within a semiconductor package

Wafer level chip scale package with exposed thick bottom metal

Semiconductor package

Bonded structures for package and substrate

Semiconductor packages having through electrodes and methods for fabricating the same

Method of manufacturing semiconductor device including grinding semiconductor wafer

Method of forming a reliable microelectronic assembly

Alignment in the packaging of integrated circuits

Ball height control in bonding process

Method for producing contact areas on a semiconductor substrate

Stack type semiconductor package

Package with solder regions aligned to recesses

Semiconductor package

Electronic circuit arrangement and method of manufacturing the same

Semiconductor device and method for fabricating the same

Packaging methods and packaged semiconductor devices

Memory module in a package

SEMICONDUCTOR DEVICE AND MICROPHONE

Semiconductor device and method of manufacturing the same

Method of making a pillar structure having a non-metal sidewall protection structure

Method of making a semiconductor device package

Pillar bumps and process for making same

Semiconductor device and method for manufacturing same

Semiconductor device with overlapped lead terminals

SEMICONDUCTOR DEVICE

Semiconductor device and manufacturing method thereof

Semiconductor device with bumps and display device module incorporating the same

Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die

Hybrid packaged lead frame based multi-chip semiconductor device with multiple semiconductor chips and multiple interconnecting structures

Semiconductor device

Semiconductor device

Method of fabricating semiconductor apparatus with through-silicon via and method of fabricating stack package including the semiconductor chip

Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant

Semiconductor package and method of manufacturing the same

Semiconductor device

Semiconductor die assemblies and semiconductor devices including same

Semiconductor chip, semiconductor apparatus having the same and method of arranging the same

Electroplating baths of silver and tin alloys

Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices

Forming of an electric connection of the via type