Fan-out package structure and methods for forming the same

Semiconductor package with single sided substrate design and manufacturing methods thereof

Semiconductor package including a substrate with a stepped sidewall structure

Integrated circuit structure and method for reducing polymer layer delamination

Semiconductor structure with sacrificial anode and passivation layer and method for forming

Surface mountable electronic component

TSV structures and methods for forming the same

Copper pillar bump with cobalt-containing sidewall protection layer

Techniques for fabricating fine-pitch micro-bumps

Fabrication method of semiconductor package

Compliant interconnects in wafers

Semiconductor device comprising mold for top side and sidewall protection

Method for bonding wafers and structure of bonding part

Thermal dissipation through seal rings in 3DIC structure

Semiconductor package

Semiconductor device with through-substrate via covered by a solder ball and related method of production

Interconnect structure for wafer level package

Semiconductor device and method of forming insulating layer around semiconductor die

Method of making a conductive pillar bump with non-metal sidewall protection structure

Method of manufacturing semiconductor device

Methods of fabricating semiconductor stack packages

Semiconductor device and method of forming adhesive material to secure semiconductor die to carrier in WLCSP

Methods of forming 3-D circuits with integrated passive devices

Composite reconstituted wafer structures

Chip package and method for forming the same

Semiconductor device

Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with semiconductor chips

Composite reconstituted wafer structures

Composite reconstituted wafer structures

Semiconductor device including DC-DC converter

Packaging process tools and packaging methods for semiconductor devices

QFN/SON-Compatible Package

Chip package and method for forming the same

Electronic component-embedded module

Testing of semiconductor chips with microbumps

Semiconductor device having stacked chips, a re-distribution layer, and penetration electrodes

Semiconductor device having under-bump metallization (UBM) structure and method of forming the same

Semiconductor device and method of forming duplex plated bump-on-lead pad over substrate for finer pitch between adjacent traces

Metal bump structure for use in driver IC and method for forming the same

Metal bump structure for use in driver IC and method for forming the same

Package structure and fabrication method thereof

Electrostatic discharge diode

Image pickup device and method for producing the same

Power semiconductor device with a double metal contact

Removable indicator structure in electronic chips of a common substrate for process adjustment

Multiple band multiple mode transceiver front end flip-chip architecture and circuitry with integrated power amplifiers

Wafer backside interconnect structure connected to TSVs

Semiconductor device and method for fabricating the same

Semiconductor device and method of forming stacked semiconductor die and conductive interconnect structure through an encapsulant

Metal bump joint structure and methods of forming

Hybrid-integrated photonic chip package with an interposer

Hybrid-integrated photonic chip package with an interposer

Stackable package by using internal stacking modules

Reliable packaging and interconnect structures

Disabling electrical connections using pass-through 3D interconnects and associated systems and methods

Semiconductor device and method of forming stress-reduced conductive joint structures

Semiconductor device and method of forming high routing density interconnect sites on substrate

Contact pads with sidewall spacers and method of making contact pads with sidewall spacers

Packaged semiconductor devices and packaging devices and methods

Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer

Semiconductor package

High quality factor filter implemented in wafer level packaging (WLP) integrated device

Through-substrate vias and methods for forming the same

Wafer process for molded chip scale package (MCSP) with thick backside metallization

Semiconductor device and method for manufacturing same

Wafer backside interconnect structure connected to TSVs

Semiconductor device and a method of manufacturing the same

Semiconductor device, semiconductor package, and electronic system

Semiconductor package having IC dice and voltage tuners

Wafer level array of chips and method thereof

Apparatus related to an improved package including a semiconductor die

Layout structure of heterojunction bipolar transistors

Adjusting sizes of connectors of package components

Chip interposer, semiconductor device, and method for manufacturing a semiconductor device

Semiconductor package

Warpage control for flexible substrates

Multi-layer power converter with devices having reduced lateral current

Semiconductor device and method of forming conductive vias using backside via reveal and selective passivation

Semiconductor device manufacturing method and semiconductor device

Chip and manufacturing method thereof

Semiconductor device and stacked semiconductor device

Through-wafer via device and method of manufacturing the same

Method apparatus and material for radio frequency passives and antennas

Method for manufacturing electronic devices

Semiconductor device and manufacturing method thereof

Semiconductor device, method for manufacturing same, and electronic component

Scheme for connector site spacing and resulting structures

Semiconductor device and method of forming shielding layer over active surface of semiconductor die

Junction structure for an electronic device and electronic device

Through silicon via with embedded barrier pad

Method of mounting semiconductor element, and semiconductor device

System and method of sensing current in a power semiconductor device

Semiconductor device having a through-substrate via

Semiconductor device and manufacturing method thereof

Chip diode and diode package

Semiconductor device, method for manufacturing the same, and electronic device

Method for forming termination structure for gallium nitride Schottky diode

Method of manufacturing semiconductor device

Semiconductor device and semiconductor package

Semiconductor package and printed circuit board

Component built-in board and method of manufacturing the same, and component built-in board mounting body

Method and apparatus of ESD protection in stacked die semiconductor device

Laser die backside film removal for integrated circuit (IC) packaging

Three-dimensional semiconductor architecture

Wafer level chip scale packaging intermediate structure apparatus and method

Stress tuning for reducing wafer warpage

Fan-out interconnect structure and method for forming same

Semiconductor device and method of forming WLCSP with semiconductor die embedded within interconnect structure

Conductive line system and process

Package on-package joint structure with molding open bumps

Semiconductor device and method of forming a dual UBM structure for lead free bump connections

Packaging devices, methods of manufacture thereof, and packaging methods

Integrated circuit structure having dies with connectors

Surface treatment in electroless process for adhesion enhancement

Method for manufacturing a semiconductor chip with each contact pad having a pad cell associated therewith

Semiconductor package assembly with decoupling capacitor

Package on-package with cavity in interposer

Power overlay structure and method of making same

Semiconductor device including RDL along sloped side surface of semiconductor die for Z-direction interconnect

Microelectronic elements with master/slave configurability

Method for making a sensor device using a graphene layer

System and method for an improved interconnect structure

Transfer substrate for forming metal wiring and method for forming metal wiring with the transfer substrate

Interconnect structures and methods of forming same

Waveguide and semiconductor packaging

Fan-out and heterogeneous packaging of electronic components

Bonding structure of semiconductor package, method for fabricating the same, and stack-type semiconductor package

Semiconductor Device and Method of Forming Sacrificial Adhesive Over Contact Pads of Semiconductor Die

Wiring substrate for a semiconductor device having differential signal paths

Packaging devices and methods of manufacture thereof

Package having substrate with embedded metal trace overlapped by landing pad

Directly sawing wafers covered with liquid molding compound

Pad defined contact for wafer level package

Vertical gallium nitride Schottky diode

Fabrication method of wiring structure for improving crown-like defect

Three-dimensional integrated circuit (3DIC)

Copper nanorod-based thermal interface material (TIM)

Systems and methods for testing and packaging a superconducting chip

Method of forming bump structure

Enhanced stacked microelectronic assemblies with central contacts

Bumpless build-up layer package with pre-stacked microelectronic devices

Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV

Electronic device comprising at least a chip enclosed in a package and a corresponding assembly process

Semiconductor device and method of forming micro-vias partially through insulating material around bump interconnect

Semiconductor bonding structure

Semiconductor device including a plurality of magnetic shields

Wafer level chip scale package and process of manufacture

Etching agent for copper or copper alloy

Semiconductor package and method of forming the same

3D semiconductor device

Component built-in board and method of manufacturing the same, and mounting body

Semiconductor device and method of embedding bumps formed on semiconductor die into penetrable adhesive layer to reduce die shifting during encapsulation

Chip package and method for forming the same

Interconnect joint protective layer apparatus and method

Front side copper post joint structure for temporary bond in TSV application

Using interrupted Through-Silicon-Vias in integrated circuits adapted for stacking

Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief

Isolation structure for stacked dies

Semiconductor device with conductive pillars having recesses or protrusions to detect interconnect continuity between semiconductor die and substrate

Copper pillar full metal via electrical circuit structure

Method and apparatus providing integrated circuit having redistribution layer with recessed connectors

Structure and method of forming a pad structure having enhanced reliability

Semiconductor packages and methods of packaging semiconductor devices

Semiconductor device, semiconductor package, and electronic device

Method for forming a thin semiconductor device

Flip-chip hybridization of microelectronic components using suspended fusible resistive connection elements

Stack package and method of manufacturing stack package

Integrated circuit film and method of manufacturing the same

3D semiconductor package interposer with die cavity

BBUL material integration in-plane with embedded die for warpage control

Mounting structure and manufacturing method for same

Package-on-package device

3D integrated circuit package with through-mold first level interconnects

Semiconductor device including a solder and method of fabricating the same

Semiconductor device and manufacturing method of the same

Electrical connectivity of die to a host substrate

Semiconductor device

Method of making a die with recessed aluminum die pads

Methods of processing substrates

Microelectronic package with stacked microelectronic units and method for manufacture thereof

Soldering device, soldering method, and substrate and electronic component produced by the soldering device or the soldering method

Circuit module and method of manufacturing the same

Method of manufacturing semiconductor device capable of enhancing bonding strength between connection terminal and electrode

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages

Chip package with improved heat dissipation and manufacturing method thereof

Semiconductor package having a cap unit with concave portion and method of manufacturing the same

Flattened substrate surface for substrate bonding

3D assembly for interposer bow

Stacked microelectronic assembly with TSVS formed in stages and carrier above chip

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

Methods and arrangements relating to semiconductor packages including multi-memory dies

Semiconductor device and semiconductor module

Active chip on carrier or laminated chip having microelectronic element embedded therein

Through silicon via structure

Methods and apparatus of packaging of semiconductor devices

Chip package and method for forming the same

Semiconductor chip package and method for manufacturing thereof

Integration of laminate MEMS in BBUL coreless package

Low-stress TSV design using conductive particles

Bump structural designs to minimize package defects

Package on package structures and methods for forming the same

Microelectronic assembly having a heat spreader for a plurality of die

Extended redistribution layers bumped wafer

Wafer-level packaging mechanisms

Method for manufacturing a semiconductor device having multiple heat sinks

Sensor package

Treatment method of electrodeposited copper for wafer-level-packaging process flow

Method of manufacturing semiconductor device

Stacked semiconductor package including connections electrically connecting first and second semiconductor packages

Manufacturing method for semiconductor package, semiconductor package, and semiconductor device

Semiconductor package and method for fabricating base for semiconductor package

Forming interconnect structures using pre-ink-printed sheets

Bumps for chip scale packaging including under bump metal structures with different diameters

Elongated bump structures in package structure

Metal routing architecture for integrated circuits

Integrated circuit package

System and method for an improved fine pitch joint

Semiconductor device manufacturing method

Stub minimization using duplicate sets of signal terminals

Method of manufacturing semiconductor device, block stacked body, and sequential stacked body

Semiconductor device including passivation layer encapsulant

Metal core solder ball and heat dissipation structure for semiconductor device using the same

Package on package (PoP) bonding structures

Post-passivation interconnect structure and method of forming the same

Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages

Semiconductor device with through silicon via and alignment mark

Guard ring design for maintaining signal integrity

Method to integrate different function devices fabricated by different process technologies

Integrated circuit and method for fabricating an integrated circuit equipped with a temperature probe

Method for bonding of group III-nitride device-on-silicon and devices obtained thereof

Semiconductor package

Semiconductor device and method of making bumpless flipchip interconnect structures

Apparatuses and methods to enhance passivation and ILD reliability

Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties

Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form

Semiconductor device and method of simultaneous molding and thermalcompression bonding

Semiconductor chip and semiconductor apparatus with embedded capacitor

Semiconductor image sensor module and method of manufacturing the same

Devices and systems for power conversion circuits

Substrate contact opening

Semiconductor wiring patterns

Methods and apparatus for package with interposers

Routing layer for mitigating stress in a semiconductor die

Pillar on pad interconnect structures, semiconductor devices including same and related methods

Flip chip package structure and fabrication process thereof

Bump structures for semiconductor package

Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices

Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages

Semiconductor device and method of forming low profile fan-out package with vertical interconnection units

Semiconductor package and method for routing the package

Apparatus for package reinforcement using molding underfill

Chip-embedded printed circuit board and semiconductor package using the PCB, and manufacturing method of the PCB

Stacked type power device module

Method and system for producing component mounting board

Carrier, semiconductor package and fabrication method thereof

Chip package and method for forming the same

Method of manufacturing chip-stacked semiconductor package

Advanced device assembly structures and methods

Stacked packaging using reconstituted wafers

Stress-resilient chip structure and dicing process

Semiconductor package and method for fabricating base for semiconductor package

Semiconductor device including alternating source and drain regions, and respective source and drain metallic strips

Semiconductor device including gate drivers around a periphery thereof

Semiconductor device including a redistribution layer and metallic pillars coupled thereto

Test structures for post-passivation interconnect

Method of manufacturing semiconductor device

Multi-dimensional integrated circuit structures and methods of forming the same

Semiconductor device using EMC wafer support system and fabricating method thereof

Configurable interposer

Bond pad configurations for controlling semiconductor chip package interactions

Integration of chips and silicon-based trench capacitors using low parasitic silicon-level connections

Method for producing a structure for microelectronic device assembly

Packaged microelectronic components

Interconnect arrangement for hexagonal attachment configurations

Semiconductor device and method for producing the same

Semiconductor memory chips and stack-type semiconductor packages including the same

Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices

Logic die and other components embedded in build-up layers

Organic thin film passivation of metal interconnections

Method for forming package-on-package structure

Chip arrangements and methods for manufacturing a chip arrangement

Power voltage supply apparatus for three dimensional semiconductor

Low profile surface mount package with isolated tab

Microelectronic assembly with thermally and electrically conductive underfill

Interconnection structure of package structure and method of forming the same

Semiconductor device and manufacturing method thereof

Interconnection structure having a via structure

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Connector design for packaging integrated circuits

Semiconductor device having conductive pads and a method of manufacturing the same

Plasma treatment for semiconductor devices

Semiconductor device, semiconductor integrated circuit device, and electronic device

Solder fatigue arrest for wafer level package

MULTI-CHIP MODULE CONNECTION BY WAY OF BRIDGING BLOCKS

Stacked chip-on-board module with edge connector

Metal pad structure over TSV to reduce shorting of upper metal layer

Devices, systems and methods using through silicon optical interconnects

Method of forming a plurality of bumps on a substrate and method of forming a chip package

Electrostatic discharge protection for three dimensional integrated circuit

Expanded semiconductor chip and semiconductor device