ClassID:

209549

H01L2224/061 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas Disposition

Sub-classes:
Recent Application in this class:
#1
20250112193
2025-04-03

SEMICONDUCTOR PACKAGE

#2
20240429205
2024-12-26

SEMICONDUCTOR PACKAGE WITH INCREASED THERMAL RADIATION EFFICIENCY

#3
20240290738
2024-08-29

SEMICONDUCTOR DEVICE

#4
20240178193
2024-05-30

SEMICONDUCTOR PACKAGES WITH PASS-THROUGH CLOCK TRACES AND ASSOCIATED SYSTEMS AND METHODS

#5
20240105558
2024-03-28

SEMICONDUCTOR DEVICE

#6
20240063158
2024-02-22

METHOD OF MAKING SEMICONDUCTOR STRUCTURE INCLUDING BUFFER LAYER

#7
20240062819
2024-02-22

NONVOLATILE MEMORY DEVICE AND MEMORY PACKAGE INCLUDING THE SAME

#8
20240006357
2024-01-04

SEMICONDUCTOR DEVICE

#9
20230048780
2023-02-16

Semiconductor packages with pass-through clock traces and associated systems and methods

#10
20220367402
2022-11-17

Semiconductor package

#11
20220310540
2022-09-29

Silicon photonic interposer with two metal redistribution layers

#12
20220293566
2022-09-15

Semiconductor package with increased thermal radiation efficiency

#13
20220208704
2022-06-30

Semiconductor structure including buffer layer

#14
20200321296
2020-10-08

Method of designing a layout, method of making a semiconductor structure and semiconductor structure

#15
20200075525
2020-03-05

Semiconductor device

#16
20200043892
2020-02-06

Chip packages and methods of manufacture thereof

#17
20200035585
2020-01-30

Multiple sized bump bonds

#18
20190148322
2019-05-16

Semiconductor device with post passivation structure

#19
20180315723
2018-11-01

Semiconductor device with post passivation structure and fabrication method therefor

#20
20180082970
2018-03-22

Semiconductor device

#21
20170301649
2017-10-19

Chip packages and methods of manufacture thereof

#22
20160268227
2016-09-15

Method of manufacturing connector structures of integrated circuits

#23
20160172332
2016-06-16

Memory module in a package

#24
20160111363
2016-04-21

Electrical connections for chip scale packaging

#25
20160104684
2016-04-14

Semiconductor memory device having pads

#26
20160071817
2016-03-10

Method for bonding metallic contact areas with solution of a sacrificial layer applied on one of the contact areas

#27
20150340341
2015-11-26

Package systems

#28
20150303160
2015-10-22

Connector structures of integrated circuits

#29
20150137349
2015-05-21

Semiconductor device and manufacturing method thereof

#30
20150097287
2015-04-09

Electrical connections for chip scale packaging

#31
20150076703
2015-03-19

Semiconductor memory device having pads

#32
20150076614
2015-03-19

Semiconductor memory device having pads

#33
20150053666
2015-02-26

Semiconductor device including asymmetric electrode arrangement

#34
20140367866
2014-12-18

Memory module in a package

#35
20140231987
2014-08-21

Connector structures of integrated circuits

#36
20140170849
2014-06-19

Package systems and manufacturing methods thereof

#37
20140061933
2014-03-06

Wire bond splash containment

#38
20130228897
2013-09-05

Electrical connections for chip scale packaging

#39
20130147052
2013-06-13

Offset of contact opening for copper pillars in flip chip packages

#40
20130119534
2013-05-16

Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump

#41
20130105977
2013-05-02

Electronic device and method for fabricating an electronic device

#42
20130093079
2013-04-18

Connector structures of integrated circuits

#43
20130087892
2013-04-11

Electrical connection for chip scale packaging

#44
20130075872
2013-03-28

Metal pad structures in dies

#45
20130015592
2013-01-17

Bond pad configurations for semiconductor dies

#46
20130015590
2013-01-17

Memory module in a package

#47
20120280399
2012-11-08

Buffer pad in solder bump connections and methods of manufacture

#48
20120221759
2012-08-30

Semiconductor device having a bus configuration which reduces electromigration

#49
20120217636
2012-08-30

Ni plating of a BLM edge for Pb-free C4 undercut control

#50
20120119362
2012-05-17

Ni plating of a BLM edge for Pb-free C4 undercut control

#51
20120098127
2012-04-26

Power/ground layout for chips

#52
20120086127
2012-04-12

Package systems having a eutectic bonding material and manufacturing methods thereof

#53
20120086126
2012-04-12

Package systems having an opening in a substrate thereof and manufacturing methods thereof

#54
20120061828
2012-03-15

Semiconductor device having metal posts non-overlapping with other devices and layout method of semiconductor device

#55
20120049351
2012-03-01

Package substrate having main dummy pattern located in path of stress

#56
20110291271
2011-12-01

Semiconductor device with grounding conductor film formed on upper surface of dielectric film formed above integrated circuit

#57
20110108981
2011-05-12

Redistribution layer enhancement to improve reliability of wafer level packaging

#58
20100071946
2010-03-25

Electronic component mounting structure

#59
20100044872
2010-02-25

Semiconductor memory device having pads

#60
20090196011
2009-08-06

Device mounting board and manufacturing method therefor, and semiconductor module

#61
20070200239
2007-08-30

Redistribution connecting structure of solder balls