209551 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas; Disposition Layout
LIGHTING DEVICE AND LAMP COMPRISING SAME
#2INDUCTOR STRUCTURES IN HYBRID BONDED DEVICES
#3V-BONDING USING DOUBLE STACKED STAND-OFF-STITCH FOR IMPROVED RF PERFORMANCE
#4INTEGRATED CIRCUIT DIE STACK WITH A BRIDGE DIE
#5SEMICONDUCTOR DEVICE
#6Semiconductor Interconnect Structure and Method
#7BACKPLANE AND GLASS-BASED CIRCUIT BOARD
#8SEMICONDUCTOR DEVICE HAVING ELECTRODE PADS ARRANGED BETWEEN GROUPS OF EXTERNAL ELECTRODES
#9SEMICONDUCTOR DEVICE HAVING ELECTRODE PADS ARRANGED BETWEEN GROUPS OF EXTERNAL ELECTRODES
#10QUASI-MONOLITHIC DIE ARCHITECTURES
#11Shifted via-chain electrical-test measurements for hybrid bonding alignment correlation
#123D Packaging Heterogeneous Area Array Interconnections
#13LIGHTING DEVICE AND LAMP COMPRISING SAME
#14Semiconductor device
#15Universal interposer for a semiconductor package
#16Semiconductor structure comprising up-narrow and down-wide openings and forming method thereof
#17Structure of semiconductor device
#18FLIP-CHIP LIGHT EMITTING DIODE (LED) DEVICE
#19SEMICONDUCTOR PACKAGES
#20Semiconductor device and a method of manufacturing thereof
#21Semiconductor interconnect structure and method
#22Semiconductor device having electrode pads arranged between groups of external electrodes
#23Semiconductor device and method of manufacturing
#24Semiconductor device and method of manufacturing the same
#25Multichip package manufacturing process
#26Semiconductor device
#27Structure of semiconductor device and method for bonding two substrates
#28Semiconductor package including semiconductor chip having point symmetric chip pads
#29Semiconductor device and a method of manufacturing thereof
#30MULTI-ACCESS MEMORY SYSTEM AND A METHOD TO MANUFACTURE THE SYSTEM
#31Semiconductor device and method of manufacturing
#32Semiconductor device having electrode pads arranged between groups of external electrodes
#33Semiconductor device and a method of manufacturing thereof
#34Plurality of lead frames electrically connected to inductor chip
#35Semiconductor interconnect structure and method
#36Stacked semiconductor package having mold vias and method for manufacturing the same
#37Apparatuses comprising semiconductor dies in face-to-face arrangements
#38Semiconductor package including multiple semiconductor chips and method of manufacturing the semiconductor package
#39Bond structures and the methods of forming the same
#40Semiconductor device and method of manufacturing
#41SEMICONDUCTOR PACKAGE
#42Semiconductor device and a method of manufacturing thereof
#43Semiconductor device having electrode pads arranged between groups of external electrodes
#44Electronic module with sealing resin
#45Offset test pads for WLCSP final test
#46Electronic assembly that includes a bridge
#47Stacked semiconductor package having mold vias and method for manufacturing the same
#48Semiconductor device with first and second semiconductor chips connected to insulating element
#49Semiconductor device
#50SEMICONDUCTOR DEVICE
#51Semiconductor device and its manufacturing method
#52Semiconductor device including plural semiconductor chips
#53Wire bonded wide I/O semiconductor device
#54Bond structures and the methods of forming the same
#55Semiconductor device
#56Semiconductor device
#57Semiconductor package including stacked semiconductor chips electrically connected to redistribution layers
#58Semiconductor device and manufacturing method thereof
#59Semiconductor device and method of manufacturing the same
#60SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#61Semiconductor packaging with reduced cracking defects
#62Semiconductor device with modified pad spacing structure
#63Semiconductor device and a method of manufacturing thereof
#64Package substrate with double sided fine line RDL
#65Semiconductor device having electrode pads arranged between groups of external electrodes
#66Multi-access memory system and a method to manufacture the system
#67Bond structures and the methods of forming the same
#68Semiconductor device with decreased overlapping area between redistribution lines and signal lines
#69Bonding pad arrangement design for multi-die semiconductor package structure
#70Packaged device with additive substrate surface modification
#71Transistors having offset contacts for reduced off capacitance
#72Semiconductor device having electrode pads arranged between groups of external electrodes
#73Reduced volume interconnect for three-dimensional chip stack
#74Method and apparatus for flip chip packaging co-design and co-designed flip chip package
#75IGBT device and method for packaging whole-wafer IGBT chip
#76Semiconductor device and its manufacturing method
#77Semiconductor device
#78Bond pad structure for low temperature flip chip bonding
#79Semiconductor memory device having pads
#80Packaged device with additive substrate surface modification
#81Semiconductor device including semiconductor chips stacked over substrate
#82Semiconductor device and manufacturing method of semiconductor device
#83Bonding pad arrangment design for multi-die semiconductor package structure
#84Semiconductor chip having different conductive pad widths and method of making layout for same
#85Single inline no-lead semiconductor package
#86Integrated circuit device
#87Semiconductor device and method of manufacturing the same
#88Semiconductor device
#89PACKAGE STRUCTURE
#90Semiconductor package with thermal via and method for fabrication thereof
#91Semiconductor device
#92Sealing structure for a bonded wafer and method of forming the sealing structure
#93Semiconductor device
#94Semiconductor device
#95Method for co-designing flip-chip and interposer
#96Monolithic bidirectional silicon carbide switching devices
#97Semiconductor device including asymmetric electrode arrangement
#98Semiconductor device and method of manufacturing the same
#99Semiconductor device and method for manufacturing the same
#100Floating bond pad for power semiconductor devices
#101Semiconductor device
#102Display panel, chip on film and display device including the same
#103Semiconductor device and method of manufacturing the same
#104Monolithic bidirectional silicon carbide switching devices
#105Chip stack packages, system in packages including the same, and methods of operating the same
#106Semiconductor device and method of manufacturing the same
#107Semiconductor package structure and manufacturing method thereof
#108Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump
#109Electronic device and method for fabricating an electronic device
#110Semiconductor device including conductive lines and pads
#111System on a chip with interleaved sets of pads
#112Manufacturing method of semiconductor device, and semiconductor device
#113Semiconductor device having semiconductor substrate electrode pads, and external electrodes
#114Contact Array for Substrate Contacting
#115Integrated circuit package and physical layer interface arrangement
#116Semiconductor chip having different pad width to UBM width ratios and method of manufacturing the same
#117Massively parallel interconnect fabric for complex semiconductor devices
#118Semiconductor device having metal posts non-overlapping with other devices and layout method of semiconductor device
#119WAFER-LEVEL PACKAGE USING STUD BUMP COATED WITH SOLDER
#120Thermal enhancement for multi-layer semiconductor stacks
#121Circuit Device
#122Semiconductor device for driving electric motor
#123Microelectronic packages with dual or multiple-etched flip-chip connectors
#124SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#125SEMICONDUCTOR DEVICE WITH A VARIABLE INTEGRATED CIRCUIT CHIP BUMP PITCH
#126Universal IO unit, associated apparatus and method
#127Semiconductor device having a wafer level chip size package structure
#128Semiconductor package and method of packaging semiconductor devices
#129Semiconductor device having integral structure of contact pad and conductive line
#130SEMICONDUCTOR DEVICE
#131Wafer level package using stud bump coated with solder
#132Semiconductor memory device having pads
#133Electronic Device and Method of Manufacturing Same
#134Semiconductor die with die pad pattern
#135Driving chip, driving chip package having the same, display apparatus having the driving chip, and method thereof
#136Semiconductor device
#137Semiconductor device including a particular dummy terminal
#138Semiconductor device
#139Apparatus and methods for constructing antennas using wire bonds as radiating elements
#140Semiconductor package
#141Semiconductor device including optional pad interconnect
#142Chip packaging structure and manufacturing method thereof