209544 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
Sub-classes:NON-CONTINUOUS PAD STRUCTURE FOR POWER SEMICONDUCTOR DEVICES AND POWER SEMICONDUCTOR DEVICES INCLUDING NON-CONTINUOUS PAD STRUCTURES
#2SEMICONDUCTOR DEVICE
#3Connection wiring
#4Power semiconductor module
#5Semiconductor device
#6Semiconductor chip and semiconductor device provided with same
#7Semiconductor device and IO-cell
#8CHIP ON FILM, FLEXIBLE DISPLAY PANEL AND DISPLAY DEVICE
#9Semiconductor device and semiconductor chip
#10Semiconductor sensor assembly for harsh media application
#11Semiconductor device and IO-cell
#12Integrated circuit and transmission and reception apparatus
#13Warm white LED with stacked wafers and fabrication method thereof
#14Semiconductor device including a cap substrate on a side wall that is disposed on a semiconductor substrate
#15Semiconductor device and method for manufacturing semiconductor device
#16DIE, WAFER AND METHOD OF PROCESSING A WAFER
#17Wireless communication system
#18Semiconductor integrated circuit
#19SEMICONDUCTOR INTEGRATED CIRCUIT
#20Apparatus with a multi-layer coating and method of forming the same
#21Wireless communication system
#22Wireless communication system
#23SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
#24Method and apparatus for scaling I/O-cell placement during die-size optimization
#25Wireless communication system
#26Layout and process to contact sub-lithographic structures
#27Semiconductor memory device and semiconductor device
#28Layout and process to contact sub-lithographic structures
#29Wireless communication system
#30Wireless communication system
#31Semiconductor wafer and testing method therefor
#32Semiconductor bare chip, method of recording ID information thereon, and method of identifying the same
#33Semiconductor device, and wiring-layout design system for automatically designing wiring-layout in such semiconductor device