209602 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bump connectors; Manufacturing methods related thereto; Manufacturing methods; Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for protecting parts during manufacture
SEMICONDUCTOR DEVICE WITH SOLDER ON PILLAR
#2STRUCTURES FOR LOW TEMPERATURE BONDING USING NANOPARTICLES
#3METHOD FOR PRODUCING SOLDER BUMPS ON A SUPERCONDUCTING QUBIT SUBSTRATE
#4SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THEREOF
#5Fan-out interconnect integration processes and structures
#6Structures for low temperature bonding using nanoparticles
#7METHOD FOR MAKING SEMICONDUCTOR DEVICE
#8Semiconductor device with solder on pillar
#9Forming Recesses in Molding Compound of Wafer to Reduce Stress
#10WAFER PROCESSING SHEET AND WAFER PROCESSING METHOD
#11Methods for low temperature bonding using nanoparticles
#12PACKAGING STRUCTURE AND FORMATION METHOD THEREOF
#13Method and apparatus of processor wafer bonding for wafer-scale integrated supercomputer
#14Structures and methods for low temperature bonding using nanoparticles
#15Semiconductor device and method
#16Forming recesses in molding compound of wafer to reduce stress
#17Bump structure manufacturing method
#18Structures and methods for low temperature bonding using nanoparticles
#19Metal bonding pads for packaging applications
#20Semiconductor device and method
#21Semiconductor devices
#22Circuit module and manufacturing method therefor
#23Fan-out interconnect integration processes and structures
#24Semiconductor device having first and second electrode layers electrically disconnected from each other by a slit
#25Semicondcutor device and manufacturing method thereof
#26Semiconductor device and semiconductor device manufacturing method
#27Metal bonding pads for packaging applications
#28Structures and methods for low temperature bonding using nanoparticles
#29Protective tape and method for manufacturing semiconductor device using the same
#30Method for manufacturing semiconductor device
#31Semiconductor device and semiconductor device manufacturing method
#32Semiconductor device having first and second electrode layers electrically disconnected from each other by a slit
#33Sintering materials and attachment methods using same
#34Semiconductor device and semiconductor device manufacturing method
#35Structures and methods for low temperature bonding using nanoparticles
#36DRY-REMOVABLE PROTECTIVE COATINGS
#37Semiconductor devices and methods of forming thereof
#38Forming recesses in molding compound of wafer to reduce stress
#39Pre-package and methods of manufacturing semiconductor package and electronic device using the same
#40Method for manufacturing semiconductor device
#41Substrate structure with array of micrometer scale copper pillar based structures and method for manufacturing same
#42Conductive connections, structures with such connections, and methods of manufacture
#43Chip part and method of making the same
#44Pre-package and methods of manufacturing semiconductor package and electronic device using the same
#45Wafer process for molded chip scale package (MCSP) with thick backside metallization
#46Method for fabricating electronic device package
#47Conductive connections, structures with such connections, and methods of manufacture
#48Conductive connections, structures with such connections, and methods of manufacture
#49Dry-removable protective coatings
#50Semiconductor device structure and manufacturing method
#51Chip diode and diode package
#52Method for manufacturing semiconductor device
#53Packages with stress-reducing structures and methods of forming same
#54Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
#55Plug via formation with grid features in the passivation layer
#56Wafer level chip scale package with exposed thick bottom metal
#57Semiconductor device and manufacturing method thereof
#58Wafer process for molded chip scale package (MCSP) with thick backside metallization
#59Semiconductor device and method of forming conductive vias using backside via reveal and selective passivation
#60Chip diode and diode package
#61Method for bonding semiconductor substrates and devices obtained thereof
#62Method of manufacturing chip-stacked semiconductor package
#63Integrated circuit devices including a via structure and methods of fabricating integrated circuit devices including a via structure
#64Repairing anomalous stiff pillar bumps
#65Method for manufacturing semiconductor device
#66Semiconductor device fabrication method
#67Integrated circuit chip using top post-passivation technology and bottom structure technology
#68Method of manufacturing a semiconductor device and wafer
#69Integrated circuit devices including through-silicon-vias having integral contact pads
#70SEMICONDUCTOR CHIP INCLUDING BUMP HAVING BARRIER LAYER, AND MANUFACTURING METHOD THEREOF
#71Wafer level chip scale package with thick bottom metal exposed and preparation method thereof
#72TSV pillar as an interconnecting structure
#73Semiconductor device with solder bump formed on high topography plated Cu pads
#74Method of manufacturing semiconductor device
#75Method of manufacturing chip-stacked semiconductor package
#76Filled through-silicon via with conductive composite material
#77Semiconductor Device and Method of Making a Semiconductor Device
#78Semiconductor device and method for fabricating the same
#79Passivation layer for semiconductor device packaging
#80METHOD OF PREPARING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR DIE FOR SEMICONDUCTOR PACKAGE
#81STACKED SEMICONDUCTOR PACKAGE HAVING CONDUCTIVE VIAS AND METHOD FOR MAKING THE SAME
#82CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT
#83Semiconductor device and semiconductor device manufacturing method
#84Method of manufacturing semiconductor device
#85Integrated circuit chip using top post-passivation technology and bottom structure technology
#86Scribe-Line Through Silicon Vias
#87Electronic device package and fabrication method thereof
#88Semiconductor device with solder bump formed on high topography plated Cu pads
#89Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same
#90SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
#91Method for manufacturing semiconductor device having electrode for external connection
#92Method and apparatus for depositing coplanar microelectronic interconnectors using a compliant mold
#93Microball attachment using self-assembly for substrate bumping
#94Method of forming metallic bump on I/O pad
#95Method of forming solder bump on high topography plated Cu
#96Conductive structure for a semiconductor integrated circuit and method for forming the same
#97Method of fabricating electronic device having sacrificial anode, and electronic device fabricated by the same
#98Removing dry film resist residues using hydrolyzable membranes
#99Method and apparatus for depositing coplanar microelectronic interconnectors using a compliant mold
#100Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same