209614 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bump connectors; Manufacturing methods related thereto; Manufacturing methods by local deposition of the material of the bump connector in liquid form Screen printing, i.e. using a stencil
SEMICONDUCTOR DEVICE, MOUNTING SUBSTRATE, AND ELECTRONIC DEVICE
#2SEMICONDUCTOR PACKAGES AND METHODS FOR MAKING THE SAME
#3ELECTRONIC DEVICE AND A METHOD FOR FORMING THE SAME
#4SEMICONDUCTOR DEVICE AND WIRING BOARD
#5Semiconductor Device and Method of Making a Molded IPD-CoW
#6SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME
#7ELECTRONIC ASSEMBLIES EMPLOYING COPPER IN MULTIPLE LOCATIONS
#8SEMICONDUCTOR WAFER AND METHOD OF BALL DROP ON THIN WAFER WITH EDGE SUPPORT RING
#9LOW PRESSURE SINTERING POWDER
#10MULTI-VIEW DEPTH ESTIMATION LEVERAGING OFFLINE STRUCTURE-FROM-MOTION
#11SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#12FINGERPRINT SENSOR AND MANUFACTURING METHOD THEREOF
#13CHIP STRUCTURE, METHOD FOR MANUFACTURING CHIP STRUCTURE, AND ELECTRONIC DEVICE
#14FLUX, SUBSTRATE AND MANUFACTURING METHOD, AND DEVICE
#15CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
#16SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME
#17ELECTRONIC COMPONENT WITH HIGH COPLANARITY AND METHOD OF MANUFACTURING THE SAME
#18ELECTRONIC DEVICE
#19Electronics assemblies employing copper in multiple locations
#20Packaged die and RDL with bonding structures therebetween
#21METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
#22ELECTRONIC DEVICE AND MANUFACTURING METHOD THEREOF
#23Fingerprint sensor and manufacturing method thereof
#24ELECTRICAL CONNECTION METHOD FOR ELECTRONIC ELEMENT, AND RELATED APPARATUS THEREOF
#25Method for manufacturing electronic chips
#26Method for manufacturing electronic component
#27Semiconductor device and method of stacking semiconductor die for system-level ESD protection
#28Buffer layer(s) on a stacked structure having a via
#29Semiconductor device and manufacturing method thereof
#30Vertical inductor for WLCSP
#31Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same
#32Semiconductor wafer and method of ball drop on thin wafer with edge support ring
#33Method for forming conductive layer, and conductive structure and forming method therefor
#34Method of manufacturing circuit structure
#35Semiconductor device and semiconductor package
#36Manufacturing method for reflowed solder balls and their under bump metallurgy structure
#37Electronics assemblies employing copper in multiple locations
#38Semiconductor structure and manufacturing method thereof
#39Method of applying conductive adhesive and manufacturing device using the same
#40Method of manufacturing semiconductor device
#41Packaged die and RDL with bonding structures therebetween
#42Low pressure sintering powder
#43Semiconductor device and manufacturing method of semiconductor device
#44Method for manufacturing electronic chips
#45Method for manufacturing electronic chips
#46Connector structure and method of forming same
#47Semiconductor device bonding area including fused solder film and manufacturing method
#48Semiconductor Device and Method
#49Method for producing a solder bump on a substrate surface
#50Semiconductor structure and manufacturing method thereof
#51System-in-package with double-sided molding
#52Vertical inductor for WLCSP
#53Semiconductor device and manufacturing method thereof
#54Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
#55Multi-die package with bridge layer
#56CIRCUIT STRUCTURE AND METHOD OF MANUFACTURING THE SAME
#57Semiconductor device and method of forming a 3D integrated system-in-package module
#58System-in-package with double-sided molding
#59Fingerprint sensor and manufacturing method thereof
#60Interconnect structures for preventing solder bridging, and associated systems and methods
#61Method for forming a semiconductor package
#62Microelectronic devices including redistribution layers
#63Method of forming a solder bump structure
#64Method of applying conductive adhesive and manufacturing device using the same
#65Wafer level integration including design/co-design, structure process, equipment stress management and thermal management
#66Buffer layer(s) on a stacked structure having a via
#67Barrier for power metallization in semiconductor devices
#68Method of making semiconductor device package including conformal metal cap contacting each semiconductor die
#69Methods of forming connector pad structures, interconnect structures, and structures thereof
#70Contact structures with porous networks for solder connections, and methods of fabricating same
#71Method for manufacturing electronic package
#72Three-dimensional integrated stretchable electronics
#73Semiconductor structure and manufacturing method thereof
#74Semiconductor structure and manufacturing method thereof
#75Method of forming a solder bump structure
#76Semiconductor device and method of manufacture
#77Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same
#78Method of manufacturing semiconductor device
#79Connector structure and method of forming same
#80Semiconductor device with compressive interlayer
#81Method for manufacturing electronic package
#82Semiconductor devices and semiconductor devices including a redistribution layer
#83Conductive line system and process
#84Methods of forming connector pad structures, interconnect structures, and structures thereof
#85Packaged semiconductor devices and methods of packaging thereof
#86Manufacturing method for reflowed solder balls and their under bump metallurgy structure
#87Vertical inductor for WLCSP
#88Package with solder regions aligned to recesses
#89Interconnect structures for preventing solder bridging, and associated systems and methods
#90Wafer level flat no-lead semiconductor packages and methods of manufacture
#91Wafer level flat no-lead semiconductor packages and methods of manufacture
#92Wafer level flat no-lead semiconductor packages and methods of manufacture
#93Semiconductor device and manufacturing method of semiconductor device
#94Semiconductor device and method of manufacture
#95Semiconductor device bonding area including fused solder film and manufacturing method
#96Semiconductor device structure and manufacturing method
#97Mechanisms for forming hybrid bonding structures with elongated bumps
#98Packaging method and package structure of wafer-level system-in-package
#99Methods and structures for wafer-level system in package
#100Method for forming a semiconductor package
#101Semiconductor package
#102Wafer-level system-in-package structure and electronic apparatus thereof
#103Flux, solder paste, and method for forming solder bump
#104Semiconductor device and method of forming a 3D integrated system-in-package module
#105Compressive interlayer having a defined crack-stop edge extension
#106MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
#107INTEGRATED CIRCUIT PACKAGE COMPRISING SURFACE CAPACITOR AND GROUND PLANE
#108Tall and fine pitch interconnects
#109Semiconductor package device and method of manufacturing the same
#110Packaged die and RDL with bonding structures therebetween
#111Assembly comprising hybrid interconnecting means including intermediate interconnecting elements and sintered metal joints, and manufacturing process
#112Method of forming solder bumps
#113Integrated circuit system with carrier construction configuration and method of manufacture thereof
#114ELECTRICAL COMPONENT WITH THIN SOLDER RESIST LAYER AND METHOD FOR THE PRODUCTION THEREOF
#115Method of making fully molded peripheral package on package device
#116SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
#117Semiconductor structure and manufacturing method thereof
#118Semiconductor device and manufacturing method thereof
#119Semiconductor device including solder bracing material with a rough surface, and manufacturing method thereof
#120Semiconductor structures and methods
#121System-in-package with double-sided molding
#122Copper pillar bump structure and manufacturing method therefor
#123Semiconductor device and method of packaging
#124Semiconductor package
#125Package with solder regions aligned to recesses
#126Methods of forming connector pad structures, interconnect structures, and structures thereof
#127Light emitting device and method of fabricating the same
#128METHOD FOR PREPARING A SEMICONDUCTOR PACKAGE
#129Microelectronic package structures including redistribution layers
#130Wafer level flat no-lead semiconductor packages and methods of manufacture
#131Structures and methods to enable a full intermetallic interconnect
#132Semiconductor wafer and method of ball drop on thin wafer with edge support ring
#133Manufacturing method of semiconductor device
#134Semiconductor device
#135Apparatus and method for contactless transfer and soldering of chips using a flash lamp
#136Solder bump stretching method
#137Fully molded miniaturized semiconductor module
#138Conductive line system and process
#139Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
#140Tall and fine pitch interconnects
#141CHIP BONDING PROCESS
#142Method of forming solder bumps
#143Method of forming solder bumps
#144Semiconductor device structure and manufacturing method
#145Semiconductor device and method of forming a PoP device with embedded vertical interconnect units
#146Method of forming a solder bump structure
#147Engineered polymer-based electronic materials
#148Buffer layer(s) on a stacked structure having a via
#149Semiconductor wafer and method of ball drop on thin wafer with edge support ring
#150Lead-free solder alloy, solder joint, solder paste composition, electronic circuit board, and electronic device
#151Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
#152Conductive connections, structures with such connections, and methods of manufacture
#153Self-alignment for redistribution layer
#154Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
#155SEMICONDUCTOR DEVICE AND METHOD COMPRISING REDISTRIBUTION LAYERS
#156Semiconductor devices including conductive pillars
#157Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP
#158Three-dimensional chip stack and method of forming the same
#159Light emitting device and method of fabricating the same
#160Integrated system and method of making the integrated system
#161Electronic device and method for producing an electronic device
#162Semiconductor device and method of forming low profile fan-out package with vertical interconnection units
#163Methods and apparatus of packaging semiconductor devices
#164Semiconductor device and method of stacking semiconductor die for system-level ESD protection
#165Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
#166Connector structure and method of forming same
#167Fingerprint sensor and manufacturing method thereof
#168Semiconductor device and method of making wafer level chip scale package
#169Semiconductor device and method of forming interconnect substrate for FO-WLCSP
#170Methods for making multi-die package with bridge layer
#171Semiconductor device manufacturing method and semiconductor wafer
#172Self-aligned under bump metal
#173Methods of forming connector pad structures, interconnect structures, and structures thereof
#174Coupling inductors in an IC device using interconnecting elements with solder caps and resulting devices
#175Semiconductor device and method of forming openings through insulating layer over encapsulant for enhanced adhesion of interconnect structure
#176Mechanisms for forming hybrid bonding structures with elongated bumps
#177Package with solder regions aligned to recesses
#178Semiconductor device and method of forming DCALGA package using semiconductor die with micro pillars
#179Integrated circuit package comprising surface capacitor and ground plane
#180Wafer-level packaging sensing device and method for forming the same
#181Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package
#182Semiconductor device and manufacturing method therefor
#183Pillar design for conductive bump
#184Methods and apparatus for solder connections
#185Fully molded miniaturized semiconductor module
#186Tall and fine pitch interconnects
#187Low pressure sintering powder
#188Formation of solder and copper interconnect structures and associated techniques and configurations
#189Semiconductor device and method comprising redistribution layers
#190Method for manufacturing metal powder
#191CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
#192Solder bump stretching method for forming a solder bump joint in a device
#1933DIC stacking device and method of manufacture
#194Magnetic intermetallic compound interconnect
#195Methods of fabricating a semiconductor package structure including at least one redistribution layer
#196Method for manufacturing semiconductor package structure
#197Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area
#198Fingerprint sensor and manufacturing method thereof
#199Wire bond support structure and microelectronic package including wire bonds therefrom
#200Package on package bonding structure and method for forming the same
#201Conductive line system and process
#202Three-dimensional chip stack and method of forming the same
#203Semiconductor device and method of forming an embedded SoP fan-out package
#204Semiconductor device and manufacturing method thereof
#205Methods for forming pillar bumps on semiconductor wafers
#206Fully molded peripheral package on package device
#207Integrated WLUF and SOD process
#208Method of manufacturing a semiconductor device having scribe lines
#209Semiconductor packages and methods of forming the same
#210Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
#211Methods of forming conductive materials on semiconductor devices, and methods of forming electrical interconnects
#212Solutions and processes for removing substances from substrates
#213Manufacturing method of ultra-thin semiconductor device package assembly
#214Formation of solder and copper interconnect structures and associated techniques and configurations
#215Chip package and method for forming the same
#216Method of packaging integrated circuits
#217Photosensitive resin composition, film adhesive, adhesive sheet, adhesive pattern, semiconductor wafer with adhesive layer, and semiconductor device
#218Ball amount process in the manufacturing of integrated circuit
#219Semiconductor device including an embedded surface mount device and method of forming the same
#220Semiconductor package
#221Semiconductor device and manufacturing method thereof
#222Multi-die package with bridge layer and method for making the same
#223Semiconductor device and method comprising redistribution layers
#224Shaped and oriented solder joints
#225Semiconductor package structure with polymeric layer and manufacturing method thereof
#226Semiconductor package including an embedded surface mount device and method of forming the same
#227Packaged semiconductor devices and methods of packaging thereof
#228Method for fabricating electronic device package
#229Methods for solder for through-mold interconnect
#230Wafer level flat no-lead semiconductor packages and methods of manufacture
#231Integrated system and method of making the integrated system
#232Methods and apparatus of packaging semiconductor devices
#233Method of forming an integrated circuit device including a pillar capped by barrier layer
#234Conductive line system and process
#2353D packages and methods for forming the same
#236Method of forming a semiconductor component comprising a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer
#237Method of making a pillar structure having a non-metal sidewall protection structure and integrated circuit including the same
#238Conductive connections, structures with such connections, and methods of manufacture
#239Stacked dies with wire bonds and method
#240Semiconductor chip having different conductive pad widths and method of making layout for same
#241Stacked chip package including substrate with recess adjoining side edge of substrate and method for forming the same
#242Metal contact for semiconductor device
#243Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP
#244Metal contact for semiconductor device
#245Semiconductor package with via-coupled power transistors
#246Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
#247Semiconductor device structure and manufacturing method
#248Mechanically anchored backside C4 pad
#249Semiconductor device and method of forming WLP with semiconductor die embedded within penetrable encapsulant between TSV interposers
#250Solder paste, joining method using the same and joined structure
#251Package on package bonding structure and method for forming the same
#252Semiconductive packaging device and manufacturing method thereof
#253Semiconductor device and method of forming build-up interconnect structures over a temporary substrate
#254Solder-on-die using water-soluble resist system and method
#255Methods and apparatus for package with interposers
#256Semiconductor device and manufacturing method thereof
#257Electronic component-mounted structure, IC card and COF package
#258Device including two power semiconductor chips and manufacturing thereof
#259Mechanisms for forming package structure
#260Self-alignment for redistribution layer
#261Fabrication methods of chip device packages
#262Chip device packages and fabrication methods thereof
#263Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
#264Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration
#265Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer
#266Semiconductor device and method of forming conductive vias through interconnect structures and encapsulant of WLCSP
#267Semiconductor package and method of fabricating the same
#268Solder bump stretching method and device for performing the same
#269Three-dimensional chip stack and method of forming the same
#270Semiconductor device and method of making wafer level chip scale package
#271Conductive structure and method for forming the same
#272Solder bump forming method and apparatus
#273Semiconductor device and method of stacking semiconductor die on a fan-out WLCSP
#274Package with solder regions aligned to recesses
#275Copper post solder bumps on substrates
#276Method of making a pillar structure having a non-metal sidewall protection structure
#277Pillar bumps and process for making same
#278Pillar design for conductive bump
#279Semiconductor device
#280Method of making a conductive pillar bump with non-metal sidewall protection structure
#281Semiconductor device and method of forming duplex plated bump-on-lead pad over substrate for finer pitch between adjacent traces
#282Chip interposer, semiconductor device, and method for manufacturing a semiconductor device
#283Semiconductor device and method of forming conductive vias using backside via reveal and selective passivation
#284Solder joint flip chip interconnection
#285Method of mounting semiconductor element, and semiconductor device
#286Component built-in board and method of manufacturing the same, and component built-in board mounting body
#287Conductive line system and process
#288Wafer-level package device having high-standoff peripheral solder bumps
#289Semiconductor device including RDL along sloped side surface of semiconductor die for Z-direction interconnect
#290Bonding structure of semiconductor package, method for fabricating the same, and stack-type semiconductor package
#291Semiconductor device and method of forming micro-vias partially through insulating material around bump interconnect
#292Functional material systems and processes for package-level interconnects
#293Semiconductor device with conductive pillars having recesses or protrusions to detect interconnect continuity between semiconductor die and substrate
#294Copper pillar full metal via electrical circuit structure
#295Packaging substrate
#296Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
#297Semiconductor device and method of simultaneous molding and thermalcompression bonding
#298Copper post solder bumps on substrates
#299Methods and apparatus for package with interposers
#300Routing layer for mitigating stress in a semiconductor die