ClassID:

209727

H01L2224/16108 - CPC Classification

Classification description:

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bump connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector; Disposition the bump connector not being orthogonal to the surface

Recent Application in this class:
#1
20240047446
2024-02-08

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME

#2
20210336114
2021-10-28

Structures and methods for electrically connecting printed components

#3
20210193619
2021-06-24

Semiconductor chip stack arrangement and semiconductor chip for producing such a semiconductor chip stack arrangement

#4
20210043816
2021-02-11

Structures and methods for electrically connecting printed components

#5
20170162613
2017-06-08

Photodetector-arrays and methods of fabrication thereof

#6
20170025390
2017-01-26

Microelectronic element with bond elements to encapsulation surface

#7
20160336287
2016-11-17

Semiconductor substrate and semiconductor package structure having the same

#8
20160001488
2016-01-07

Method and device for producing and filling containers

#9
20150364446
2015-12-17

Semiconductor chip assembly and method for manufacturing the same

#10
20150108636
2015-04-23

Submount, encapsulated semiconductor element, and methods of manufacturing the same

#11
20140021596
2014-01-23

Wafer-level device packaging

#12
20130075915
2013-03-28

Integrated circuit packaging system with chip stacking and method of manufacture thereof

#13
20130015578
2013-01-17

Interconnection and assembly of three-dimensional chip packages

#14
20130009304
2013-01-10

Chip-stacked semiconductor package

#15
20120319289
2012-12-20

SEMICONDUCTOR PACKAGE

#16
20120319269
2012-12-20

Enhanced bump pitch scaling

#17
20120199960
2012-08-09

WIRE BONDING FOR INTERCONNECTION BETWEEN INTERPOSER AND FLIP CHIP DIE

#18
20100295173
2010-11-25

Composite Underfill and Semiconductor Package

#19
20100276081
2010-11-04

Method of interconnecting electronic wafers

#20
20100136747
2010-06-03

METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE

#21
20100117209
2010-05-13

MULTIPLE CHIPS ON A SEMICONDUCTOR CHIP WITH COOLING MEANS

#22
20080111229
2008-05-15

Semiconductor package

#23
20070296067
2007-12-27

Semiconductor package including connector disposed in troughhole

#24
20050218517
2005-10-06

Semiconductor flip-chip package and method for the fabrication thereof

#25
20050104027
2005-05-19

Three-dimensional integrated circuit with integrated heat sinks

#26
20050011660
2005-01-20

Method of fabricating an electronic device