Scheme for connector site spacing and resulting structures

Re-distribution Layer Via Structure and Method of Making Same

Back-side contact formation

Interconnect barrier structure and method

THREE DIMENSIONAL MICROELECTRONIC COMPONENTS AND FABRICATION METHODS FOR SAME

Chip packages and methods for manufacturing a chip package

Semiconductor Constructions and Methods of Forming Semiconductor Constructions

Semiconductor constructions and methods of planarizing across a plurality of electrically conductive posts

Chip package and method for forming the same

Low loop wire bonding

Wire-based methodology of widening the pitch of semiconductor chip terminals

Electric connecting structure comprising preferred oriented CuSngrains and method for fabricating the same

Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer

Methods of forming bonded semiconductor structures

CHIP CONNECTION STRUCTURE AND METHOD OF FORMING

Protected solder ball joints in wafer level chip-scale packaging

WSP DIE HAVING REDISTRIBUTION LAYER CAPTURE PAD WITH AT LEAST ONE VOID

Cu pillar bump with electrolytic metal sidewall protection

Method of forming an integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad

Method for testing through-silicon-via (TSV) structures

Chip package and method for forming the same

Stack of semiconductor structures and corresponding manufacturing method

Bump structure, having concave lateral sides, semiconductor package having the bump structure, and method of forming the bump structure

Electronic device packages including bump buffer spring pads and methods of manufacturing the same

Light emitting device chip scale package

Semiconductor package and methods of formation thereof

Electrochemical etching of semiconductors

Method for obtaining a palladium surface finish for copper wire bonding on printed circuit boards and IC-substrates

Electrical connection structure

3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach

Package structure and substrate bonding method

Through silicon via with embedded barrier pad

Semiconductor structure with low-melting-temperature conductive regions, and method of repairing a semiconductor structure

Method for chip packaging

Semiconductor device fabrication method capable of scribing chips with high yield

SOLDERABLE PAD FABRICATION FOR MICROELECTRONIC COMPONENTS

Chip pad resistant to antenna effect and method

Methods and apparatus for solder connections

Controlled solder-on-die integrations on packages and methods of assembling same

Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure

Cleaning methods and compositions

Method to realize flux free indium bumping

Offset interposers for large-bottom packages and large-die package-on-package structures

Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same

Method for designing a package and substrate layout

Process for direct bonding two elements comprising copper portions and portions of dielectric materials

Etching solution for copper or copper alloy

Semiconductor structures and methods of manufacture

Semiconductor packages and methods of fabricating the same

Bottom-up plating of through-substrate vias

3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias

Bonded processed semiconductor structures and carriers

STACKED SEMICONDUCTOR COMPONENTS WITH UNIVERSAL INTERCONNECT FOOTPRINT

Bonding pad structure with dense via array

Shallow via formation by oxidation

Semiconductor device

SEMICONDUCTOR CHIP DEVICE WITH FRAGMENTED SOLDER STRUCTURE PADS

Packaging device and method of making the same

Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die

Semiconductor device and method of manufacturing the same

Electromigration-resistant lead-free solder interconnect structures

Method of manufacturing a semiconductor integrated circuit device

Magnet assisted alignment method for wafer bonding and wafer level chip scale packaging

Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips

Semiconductor device and method of forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief

Conductive bump structure on substrate and fabrication method thereof

Method for manufacturing fine-pitch bumps and structure thereof

Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation

ELECTROMIGRATION-RESISTANT LEAD-FREE SOLDER INTERCONNECT STRUCTURES

Bundled memory and manufacture method for a bundled memory with an external input/output bus

Semiconductor device and method of simultaneous testing of multiple interconnects for electro-migration

Method of manufacturing a semiconductor component

Integrated circuit chip using top post-passivation technology and bottom structure technology

Inductor for post passivation interconnect

Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of FO-WLCSP

Semiconductor structure and method of forming the same

Stack semiconductor apparatus having a through silicon via and method of fabricating the same

Methods and apparatus for solder on slot connections in package on package structures

Methods and apparatus of guard rings for wafer-level-packaging

Eutectic bonding of thin chips on a carrier substrate

Semiconductor device bonding with stress relief connection pads

Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration

Semiconductor constructions

Self-aligned polymer passivation/aluminum pad

Semiconductor component that includes a protective structure

Semiconductor device including a stress buffer material formed above a low-k metallization system

Silicon carbide semiconductor device and manufacturing method thereof

Protection layers for conductive pads and methods of formation thereof

Semiconductor device and method of forming protective coating over interconnect structure to inhibit surface oxidation

Method for manufacturing semiconductor devices having a glass substrate

Electrical connections for chip scale packaging

Method for package-on-package assembly with wire bonds to encapsulation surface

Method for chip package

Mechanisms for forming connectors with a molding compound for package on package

Devices and methods related to interconnect conductors to reduce de-lamination

Devices and methods related to electrostatic discharge protection benign to radio-frequency operation

Bumping process and structure thereof

Semiconductor devices having conductive via structures and methods for fabricating the same

Methods of forming reverse side engineered III-nitride devices

Semiconductor device, method for manufacturing semiconductor device, and electronic apparatus

Method of manufacturing a semiconductor device and wafer

Post-passivation interconnect structure AMD method of forming same

Semiconductor chip comprising a plurality of contact pads and a plurality of associated pad cells

Interconnect crack arrestor structure and methods

Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same

Transfer substrate for forming metal wiring and method for forming metal wiring using said transfer substrate

Method for building vertical pillar interconnect

OPTIMIZATION OF COPPER PLATING THROUGH WAFER VIA

BUMPING PROCESS AND STRUCTURE THEREOF

Integrated Circuit Die And Method Of Fabricating

Method for forming pad in wafer with three-dimensional stacking structure

Semiconductor device and method of manufacturing the same

Multi-chip fan out package and methods of forming the same

Package assembly and method of forming the same

Semiconductor packaging structure and method

Backside integration of RF filters for RF front end modules and design structure

Biosensor capacitor

BUMPING PROCESS

Bump pad structure

Semiconductor devices with compliant interconnects

Package on package interconnect structure

Method of processing a contact pad

Bonding pad and method of making same

UBM formation for integrated circuits

Method for manufacturing an electronic device by reducing thickness of electronic members attached to a carrier

Semiconductor device having a through-substrate via

Packaged semiconductor device with a molding compound and a method of forming the same

Semiconductor package, packaging substrate and fabrication method thereof

Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief

Techniques for wafer-level processing of QFN packages

Manufacturing method of semiconductor device, processing method of semiconductor wafer, semiconductor wafer

SEMICONDUCTOR DEVICE INCLUDING THROUGH ELECTRODE AND METHOD OF MANUFACTURING THE SAME AND STACKED PACKAGE INCLUDING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP

Integrated circuit packaging system with coupling features and method of manufacture thereof

PAD OVER INTERCONNECT PAD STRUCTURE DESIGN

Leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect

Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer

Device including two power semiconductor chips and manufacturing thereof

Electrode connecting structures containing copper

Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration

Electronic device with multi-layer contact

Semiconductor devices including protected barrier layers

Method of fabricating a wafer level semiconductor package having a pre-formed dielectric layer

Electrical connection structure

Wafer level chip scale package

CONNECTING PAD PRODUCING METHOD

Active area bonding compatible high current structures

Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process

Thick film conductive composition and use thereof

Integrated circuit having staggered bond pads and I/O cells

Conductive structure and method for forming the same

Mechanisms for forming fine-pitch copper bump structures

Bumps for Chip Scale Packaging

Through-silicon via with low-K dielectric liner

Termination structure for gallium nitride schottky diode

Vertical gallium nitride Schottky diode

Method for separating a plurality of dies and a processing device for separating a plurality of dies

Semiconductor structure having lateral through silicon via

Semiconductor device

Semiconductor device

Post-passivation interconnect structure and method of forming the same

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

Method of fabricating land grid array semiconductor package

Flattened substrate surface for substrate bonding

Electronic device and method for fabricating an electronic device

TSV backside processing using copper damascene interconnect technology

WAFER LEVEL CHIP SCALE PACKAGE DEVICE AND MANUFACTURING METHOD THEROF

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

Methods of forming bump structures that include a protection layer

SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE

Semiconductor device and method of forming conductive pillar having an expanded base

Connector structures of integrated circuits

Process for forming package-on-package structures

Semiconductor structure and method for making same

Semiconductor package having an anti-contact layer

Methods of packaging semiconductor devices and structures thereof

Copper Stud Bump Wafer Level Package

Bump with protection structure

ELECTRONIC PACKAGING CONNECTOR AND METHODS FOR ITS PRODUCTION

Power management applications of interconnect substrates

Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts

SEMICONDUCTOR DEVICE

Seal ring structure with a metal pad

METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

INTEGRATED CIRCUIT AND METHOD OF MAKING

Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP

Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers

Interconnection Between Integrated Circuit and Package

Semiconductor device and method for manufacturing semiconductor device

Integrated circuit and method of making

Manufacturing method of semiconductor integrated circuit device

Semiconductor device and method of forming protection and support structure for conductive interconnect structure

Semiconductor device and method of forming protection and support structure for conductive interconnect structure

Chips having rear contacts connected by through vias to front contacts

Semiconductor integrated circuit device and method of manufacturing same

Backplate interconnect with integrated passives

Semiconductor structure and method for making same

System and method for 3D integrated circuit stacking

Low loop wire bonding

Semiconductor package with improved pillar bump process and structure

Packaging methods and structures for semiconductor devices

Pillar structure having a non-planar surface for semiconductor devices

ROUTING UNDER BOND PAD FOR THE REPLACEMENT OF AN INTERCONNECT LAYER

Die-to-die gap control for semiconductor structure and method

Self-aligned protection layer for copper post structure

Methods of fabricating semiconductor chip solder structures

Semiconductor laser mounting with intact diffusion barrier layer

MEMS device having chip scale packaging

Through silicon via layout

Method for permanent connection of two metal surfaces

Method of Multi-Chip Wafer Level Packaging

Semiconductor device having a through-substrate via

Semiconductor device, semiconductor package, method for manufacturing semiconductor device, and method for manufacturing semiconductor package

Method for inhibiting growth of intermetallic compounds

Wafer level package structure and the fabrication method thereof

Semiconductor package with under bump metallization routing

Method of fabricating a semiconductor device having recessed bonding site

Method of forming a semiconductor device with a contact pad on a sloped silicon dioxide surface

WAFER LEVEL PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Routing layer for mitigating stress in a semiconductor die

Semiconductor device comprising through-electrode interconnect

Pad structure including glue layer and non-low-k dielectric layer in BSI image sensor chips

Method of making a die with recessed aluminum die pads

Method and system for forming conductive bumping with copper interconnection

Method of manufacturing semiconductor device

WAFER LEVEL CHIP SCALE PACKAGE FOR WIRE-BONDING CONNECTION

Semiconductor device and manufacturing method therefor

Integrated circuit package including a direct connect pad, a blind via, and a bond pad electrically coupled to the direct connect pad

Electronic chip comprising connection pillars and manufacturing method

Coaxial solder bump support structure

Bump structures in semiconductor device and packaging assembly

Fused buss for plating features on a semiconductor die

Bumping process and structure thereof

Composite layered chip package

Contact pad

Interconnect pillars with directed compliance geometry

Bonding surfaces for direct bonding of semiconductor structures

Semiconductor device and a method of manufacturing the same

Solder ball contact susceptible to lower stress

Solder bump with inner core pillar in semiconductor package

Semiconductor device with solder bump formed on high topography plated Cu pads

Method of forming an inductor on a semiconductor wafer

Semiconductor device for improving electrical and mechanical connectivity of conductive pillers and method therefor

UBM etching methods for eliminating undercut

Semiconductor device, fabrication method for a semiconductor device and electronic apparatus

Forming wafer-level chip scale package structures with reduced number of seed layers

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR CHIP AND FLIP-CHIP PACKAGE COMPRISING THE SAME

Ball-limiting-metallurgy layers in solder ball structures

Electronic device

Method of manufacturing semiconductor device

Microfeature workpieces having alloyed conductive structures, and associated methods

Semiconductor constructions

Semiconductor device

Interconnect barrier structure and method

Multi-component integrated circuit contacts

Copper wire receiving pad

Electrically conductive paste, and electrically conducive connection member produced using the paste

ELECTRIC JOINT STRUCTURE AND METHOD FOR PREPARING THE SAME

MICRO PIN HYBRID INTERCONNECT ARRAY

Methods for controlling wafer curvature

Enhanced WLP for superior temp cycling, drop test and high current applications

STACKED SEMICONDUCTOR DEVICE

SEMICONDUCTOR CHIP WITH DUAL POLYMER FILM INTERCONNECT STRUCTURES

Bump structure with barrier layer on post-passivation interconnect

Semiconductor device and method of forming protective coating over interconnect structure to inhibit surface oxidation

Semiconductor device and method of forming interconnect structure over seed layer on contact pad of semiconductor die without undercutting seed layer beneath interconnect structure

Semiconductor device and manufacturing method

Die backside standoff structures for semiconductor devices

Bump structure and process of manufacturing the same

Hermetically sealed wafer packages

Back-side contact formation

Electronic device and method for producing electronic device

Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via

METHOD OF MANUFACTURING A SEMICONDUCTOR CHIP PACKAGE

Layered chip package and method of manufacturing same

Layered chip package and method of manufacturing same

Fan-out microelectronic unit WLP having interconnects comprising a matrix of a high melting point, a low melting point and a polymer material

Method for producing a protective structure

Bonded semiconductor structures and methods of forming same

Semiconductor device

Semiconductor device and method of forming a power MOSFET with interconnect structure silicide layer and low profile bump

Heterostructure containing IC and LED and method for fabricating the same

CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME

Method of fabricating semiconductor device

Implantable microelectronic device and method of manufacture

Method of manufacturing a semiconductor device

Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties

Conductive pads defined by embedded traces

Methods of forming through-substrate interconnects

Wafer-level package device

Electrical connection for chip scale packaging

Injection molded solder process for forming solder bumps on substrates

Injection molded solder process for forming solder bumps on substrates

Aluminum Bond Pad With Trench Thinning for Fine Pitch Ultra-Thick Aluminum Products

Semiconductor device having a trace comprises a beveled edge

SEMICONDUCTOR COMPONENT AND METHOD OF FABRICATING THE SAME

Semiconductor device and method of forming bump structure with multi-layer UBM around bump formation area

Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias

Semiconductor device and method of forming shielding layer over semiconductor die mounted to TSV interposer