Conductive via structure

Method of manufacturing semiconductor device

Method for producing a metal layer on a substrate and device

Electromigration immune through-substrate vias

Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit

Semiconductor device having a bonding pad and shield structure of different thickness

Method for producing a connection region on a side wall of a semiconductor body

Method for fabricating stacked semiconductor system with encapsulated through wire interconnects (TWI)

Semiconductor device and a manufacturing method thereof

Die stacking with an annular via having a recessed socket

Doping Minor Elements into Metal Bumps

Chip package and method for forming the same

Semiconductor device and method of forming dummy pillars between semiconductor die and substrate for maintaining standoff distance

EMBEDDED CAPACITOR DEVICE AND METHODS OF FABRICATION

Method of manufacturing a semiconductor component

Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die

Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die

Buffer pad in solder bump connections and methods of manufacture

Chip package and fabrication method thereof

Copper pillar bump with non-metal sidewall protection structure and method of making the same

Semiconductor structure and fabrication method thereof

Techniques for improving bond pad performance

EPOXY COATING ON SUBSTRATE FOR DIE ATTACH

Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer

Semiconductor device and method of embedding TSV semiconductor die within substrate for vertical interconnect in POP

Microelectronic chip, component containing such a chip and manufacturing method

Contact Metal for Hybridization and Related Methods

Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillar

Chip on film type semiconductor package

High voltage resistance coupling structure

Semiconductor device and manufacturing method of the same

Method of manufacturing nitride semiconductor light emitting element having thick metal bump

Etchant and method for manufacturing semiconductor device using same

Routing layer for mitigating stress in a semiconductor die

Method of making a semiconductor device having a functional capping

Active area bonding compatible high current structures

Semiconductor Device and Method of Providing Common Voltage Bus and Wire Bondable Redistribution

REINFORCED VIA FARM INTERCONNECT STRUCTURE, A METHOD OF FORMING A REINFORCED VIA FARM INTERCONNECT STRUCTURE AND A METHOD OF REDESIGNING AN INTEGRATED CIRCUIT CHIP TO INCLUDE SUCH A REINFORCED VIA FARM INTERCONNECT STRUCTURE

SEMICONDUCTOR CHIP WITH PATTERNED UNDERBUMP METALLIZATION

Etchant and method for manufacturing semiconductor device using same

Solder ball contact susceptible to lower stress

Semiconductor device and method for fabricating the same

Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods

Method for manufacturing semiconductor devices having a glass substrate

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

Semiconductor device having pad region for wire-bonding and method of manufacturing the semiconductor device

Methods for forming a semiconductor structure

Method for the production of an electronic component and electronic component produced according to this method

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Selective electromigration improvement for high current C4s

Semiconductor device and manufacturing method thereof

Method of fabricating a semiconductor chip with supportive terminal pad

Semiconductor device and method of forming pad layout for flipchip semiconductor die

LAYOUT SCHEME FOR AN INPUT OUTPUT CELL

Semiconductor apparatus, electronic device, and method of manufacturing semiconductor apparatus

Apparatuses and methods to enhance passivation and ILD reliability

Semiconductor device, method of manufacturing the same, and method of manufacturing wiring board

IC wafer having electromagnetic shielding effects and method for making the same

Devices including bond pad having protective sidewall seal

Production method for thick film metal electrode and production method for thick film resist

Protection of reactive metal surfaces of semiconductor devices during shipping by providing an additional protection layer

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM USING THE SAME

Template and pattern forming method

Semiconductor device and method of confining conductive bump material during reflow with solder mask patch

Solder bump interconnect

Semiconductor device and method for manufacturing semiconductor device

Semiconductor device and method of forming shielding layer over semiconductor die mounted to TSV interposer

Moisture barrier for a wire bond

Semiconductor device and method of forming vertical interconnect structure between semiconductor die and substrate

Apparatus and methods for reducing impact of high RF loss plating

Wire bond pad system and method

Through-hole electrode substrate and method of manufacturing the same

Interconnections for fine pitch semiconductor devices and manufacturing method thereof

Semiconductor apparatus, method for manufacturing the same and electric device

Semiconductor devices including a through-substrate conductive member with an exposed end

Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of Fo-WLCSP

Semiconductor device and method of forming conductive THV and RDL on opposite sides of semiconductor die for RDL-to-RDL bonding

Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer

PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Determining intra-die wirebond pad placement locations in integrated circuit

Bond pad structure

Semiconductor device and method of forming multi-layered UBM with intermediate insulating buffer layer to reduce stress for semiconductor wafer

Joining electrode, method of manufacturing the same, semiconductor device, and method of manufacturing the same

WAFER CHIP SCALE PACKAGE CONNECTION SCHEME

Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process

Semiconductor-on-insulator with back side connection

DEVICE MOUNTING BOARD AND METHOD OF MANUFACTURING THE SAME, SEMICONDUCTOR MODULE, AND MOBILE DEVICE

Method for mounting a semiconductor chip on a carrier

Passivation layer for semiconductor device packaging

On-Chip RF shields with front side redistribution lines

Process for forming an anti-oxidant metal layer on an electronic device

Testing of semiconductor chips with microbumps

Integrated circuit package system with post-passivation interconnection and integration

Devices containing silver compositions deposited by micro-deposition direct writing silver conductor lines

Semiconductor chip package structure, semiconductor chip and semiconductor chip group

Semiconductor-on-insulator with back side strain inducing material

METHOD OF FORMING UNDERBUMP METALLURGY STRUCTURE EMPLOYING SPUTTER-DEPOSITED NICKEL COPPER ALLOY

WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET'S)

Semiconductor device, method for manufacturing the same, and data processing device

Interconnection structure

Chip package structure with ENIG plating

Semiconductor device and method of forming stud bumps over embedded die

Method of making ferroelectric memory device with barrier layer and novolac resin passivation layer

WIRING STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE WIRING STRUCTURE

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Manufacturing method of semiconductor device and semiconductor device

COPPER-BASED METALLIZATION SYSTEM INCLUDING AN ALUMINUM-BASED TERMINAL LAYER

3D integration method using SOI substrates and structures produced thereby

Pad bonding employing a self-aligned plated liner for adhesion enhancement

Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component

Semiconductor device and method of forming column interconnect structure to reduce wafer stress

Structures for improving current carrying capability of interconnects and methods of fabricating the same

DIRECT THROUGH VIA WAFER LEVEL FANOUT PACKAGE

Semiconductor apparatus having penetration electrode and method for manufacturing the same

Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device

Structure of electrolessly palladium and gold plated films and process for making the same, assembled structure of palladium and gold plated films bonded with copper or copper-palladium wire and assembling process therefore

Electrochemical etching of semiconductors

Method for forming chip package

Forming through-silicon-vias for multi-wafer integrated circuits

PACKAGE STRUCTURE, PACKAGING SUBSTRATE AND CHIP

Chip package and method for forming the same

Device including two mounting surfaces

METHOD FOR FORMING AN OVER PAD METALIZATION (OPM) ON A BOND PAD

Warpage control features on the bottomside of TSV die lateral to protruding bottomside tips

Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure

Semiconductor device and method of forming conductive pillars in recessed region of peripheral area around the device for electrical interconnection to other devices

Chip-exposed semiconductor device

Integrated circuit chip and fabrication method

Method of manufacturing semiconductor device

Semiconductor device having a copper plug

Methods and designs for localized wafer thinning

Methods and Structures Involving Terminal Connections

Semiconductor package with a metal post and manufacturing method thereof

Three-dimensional semiconductor device

BALL GRID ARRAY METHOD AND STRUCTURE

Chip scale surface mounted semiconductor device package and process of manufacture

Chip pad resistant to antenna effect and method

CRACK REDUCTION AT METAL/ORGANIC DIELECTRIC INTERFACE

Method of fabricating a TSV for 3D packaging of semiconductor device

Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods

Semiconductor device and method of manufacturing semiconductor device

Bump structure and manufacturing method thereof

Method for chip scale package and package structure thereof

Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages

Integrated circuit package connected to a data transmission medium

Integrated circuit chip and fabrication method

Wafer-level interconnect for high mechanical reliability applications

Solder bump connections

Compliant interconnects in wafers

Semiconductor device and method of forming an inductor within interconnect layer vertically separated from semiconductor die

Chip package and method for forming the same

Methods of manufacturing a semiconductor device

Aluminum enhanced palladium CMP process

Bonding structure of semiconductor package, method for fabricating the same, and stack-type semiconductor package

Method of processing a substrate

SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF

STRUCTURES AND METHODS FOR IMPROVING SOLDER BUMP CONNECTIONS IN SEMICONDUCTOR DEVICES

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor packages and methods of manufacturing the same

Semiconductor Device with Cross-shaped Bumps and Test Pads Alignment

Semiconductor device having conductive vias and semiconductor package having semiconductor device

Semiconductor device and semiconductor package having the same

Contact Array for Substrate Contacting

Integrated circuit manufacturing method and integrated circuit

Wafer level chip package and a method of fabricating thereof

SEMICONDUCTOR SUBSTRATE AND METHOD THEREOF

Semiconductor device and method of forming passive devices

Semiconductor package

METAL LAYER FORMATION METHOD FOR DIODE CHIPS/WAFERS

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

Electrical connector between die pad and z-interconnect for stacked die assemblies

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Conductive pads defined by embedded traces

Adding cap to copper passivation flow for electroless plating

Grain refinement by precipitate formation in Pb-free alloys of tin

Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A REFRACTORY METAL CONTAINING FILM

Semiconductor device manufacturing method and semiconductor device

Contact pad

Semiconductor structure and method for making same

Electroplated posts with reduced topography and stress

Seal ring in an integrated circuit die

Etching composition for an under-bump metallurgy layer

ALUMINUM BOND PADS WITH ENHANCED WIRE BOND STABILITY

Pattern layout in semiconductor device

Semiconductor packages

Semiconductor device and method of stacking semiconductor die in mold laser package interconnected by bumps and conductive vias

Semiconductor device and method for manufacturing the same

Structure, semiconductor structure and method of manufacturing a semiconductor structure and packaging thereof

Semiconductor device and method of shielding semiconductor die from inter-device interference

Semiconductor device and method for manufacturing semiconductor device

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH ELECTRODE

Simplified copper-copper bonding

METHOD FOR PACKAGING A SEMICONDUCTOR CHIP, AND SEMICONDUCTOR PACKAGE

Integrated circuits with backside metalization and production method thereof

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

SEMICONDUCTOR DEVICE HAVING UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME

Semiconductor component having a second passivation layer having a first opening exposing a bond pad and a plurality of second openings exposing a top surface of an underlying first passivation layer

Bond pad for wafer and package for CMOS imager

Process for realizing a connecting structure

Pass-through 3D interconnect for microelectronic dies and associated systems and methods

WAFER LEVEL LED PACKAGE STRUCTURE FOR INCREASING LIGHT-EMITTING EFFICIENCY AND HEAT-DISSIPATING EFFECT AND METHOD FOR MANUFACTURING THE SAME

Method and structure for top metal formation of liquid crystal on silicon devices

Microelectronic assemblies having compliancy and methods therefor

Semiconductor chip having different pad width to UBM width ratios and method of manufacturing the same

Copper pillar bump with cobalt-containing sidewall protection

Under-bump metallization (UBM) structure and method of forming the same

Conductive pillar structure

Semiconductor die and method of forming noise absorbing regions between THVs in peripheral region of the die

Semiconductor device and the method of manufacturing the same

Method and system for forming conductive bumping with copper interconnection

Layered chip package and method of manufacturing same

Package systems having a eutectic bonding material and manufacturing methods thereof

Package systems having an opening in a substrate thereof and manufacturing methods thereof

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor device and semiconductor package having the same

Cost-effective TSV formation

Dimensionally decoupled ball limiting metalurgy

Metal wiring structures for uniform current density in C4 balls

Method for producing a metallization having two multiple alternating metallization layers for at least one contact pad and semiconductor wafer having said metallization for at least one contact pad

Sheet-molded chip-scale package

Method of Contacting a Semiconductor Substrate

Manufacturing method of semiconductor device

Semiconductor device and method of bonding different size semiconductor die at the wafer level

Semiconductor structure and method for making same

Semiconductor structure having metal oxide or nirtride passivation layer on fill layer and method for making same

Semiconductor structure and method for making same

Package for semiconductor device including guide rings and manufacturing method of the same

SEMICONDUCTOR DEVICE PROVIDED WITH REAR PROTECTIVE FILM ON OTHER SIDE OF SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD OF THE SAME

Semiconductor device and manufacturing method of the same

Method and system for improving reliability of a semiconductor device

Semiconductor device and a method of manufacturing the same

Semiconductor device and method of forming protective structure around semiconductor die for localized planarization of insulating layer

Stacked chip assembly having vertical vias

LAYER STACKS AND INTEGRATED CIRCUIT ARRANGEMENTS

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Staged via formation from both sides of chip

Multi-function and shielded 3D interconnects

Substrate bonding with metal germanium silicon material

Method for reducing UBM undercut in metal bump structures

Copper bonding compatible bond pad structure and method

Semiconductor device and manufacturing method thereof

Die structure, die arrangement and method of processing a die

Collar structure around solder balls that connect semiconductor die to semiconductor chip package substrate

Semiconductor device having pad structure with stress buffer layer

Semiconductor chip with redundant thru-silicon-vias

Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect

Semiconductor packages having increased input/output capacity and related methods

Layered chip package and method of manufacturing same

Compliant printed circuit wafer level semiconductor package

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

Die edge contacts for semiconductor devices

Semiconductor device and manufacturing method of semiconductor device

SEMICONDUCTOR DEVICE

Alignment marks in substrate having through-substrate via (TSV)

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield and a method for fabricating the same

Bump structure with underbump metallization structure and integrated redistribution layer

Semiconductor apparatus

Pillar bumps and process for making same

Conductive connection structure with stress reduction arrangement for a semiconductor device, and related fabrication method

Method of manufacturing semiconductor package

Semiconductor module system having stacked components with encapsulated through wire interconnects (TWI)

Process for making conductive post with footing profile

Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers

Seal ring structure with metal pad

Bond pad for low K dielectric materials and method for manufacture for semiconductor devices

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Package-on-package with fan-out WLCSP

Bottom source power MOSFET with substrateless and manufacturing method thereof

Alpha particle blocking wire structure and method fabricating same

Semiconductor apparatus, method of manufacturing the same, and method of manufacturing semiconductor package

Embedded wafer-level bonding approaches

ELECTRICAL OR ELECTRONIC COMPOSITE COMPONENT AND METHOD FOR PRODUCING AN ELECTRICAL OR ELECTRONIC COMPOSITE COMPONENT

Semiconductor device having a pad

Electronic device and method for production

Integrated circuit structure incorporating a conductor layer with both top surface and sidewall passivation and a method of forming the integrated circuit structure

Method of forming a memory device

Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces

Semiconductor device

Wafer level chip scale package

Methods of forming semiconductor elements using micro-abrasive particle stream

CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Doping minor elements into metal bumps

Reducing delamination between an underfill and a buffer layer in a bond structure

Semiconductor device and method of forming RDL over contact pad with high alignment tolerance or reduced interconnect pitch

Chip scale package and fabrication method thereof

Microelectronic elements having metallic pads overlying vias

Metal-contamination-free through-substrate via structure

COATING AND ELECTRONIC COMPONENT

Method of manufacturing wafer level package

Method for manufacturing semiconductor devices having a metallisation layer

Layered chip package and method of manufacturing same

Die package structure

Methods of forming bonded semiconductor structures using a temporary carrier having a weakened ion implant region for subsequent separation along the weakened region

Methods of forming bonded semiconductor structures