Conductive lines and pads and method of manufacturing thereof

BONDING PAD FOR ANTI-PEELING PROPERTY AND METHOD FOR FABRICATING THE SAME

Semiconductor device having an interconnect structure with TSV using encapsulant for structural support

Conductive sidewall for microbumps

Recessed pillar structure

Method for manufacturing semiconductor devices having a glass substrate

Substrate stand-offs for semiconductor devices

INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING REACTION BARRIER LAYERS

Solder bump with inner core pillar in semiconductor package

UBM Etching Methods

Semiconductor substrates with unitary vias and via terminals, and associated systems and methods

Wiring board and method for manufacturing the same

Multi-layer via structure

Backside processing of semiconductor devices

Methods, devices, and materials for metallization

Method of forming semiconductor die

Protecting bond pad for subsequent processing

Wiring board and method for manufacturing the same

Method for manufacture of integrated circuit package system with protected conductive layers for pads

Wafer level package (WLP) device having bump assemblies including a barrier metal

Semiconductor arrangement, semiconductor module, and method for connecting a semiconductor chip to a ceramic substrate

SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME

Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect

Semiconductor device having semiconductor substrate, and method of manufacturing the same

Protection film having a plurality of openings above an electrode pad

Layered chip package and method of manufacturing same

Semiconductor device

Laminated semiconductor substrate, laminated chip package and method of manufacturing the same

Manufacturing method for semiconductor devices

Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Integrated circuit system with recessed through silicon via pads and method of manufacture thereof

Plasma treatment for semiconductor devices

Semiconductor integrated circuit device and method of manufacturing the same

Semiconductor device with copper wire ball-bonded to electrode pad including buffer layer

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, WIRING BOARD AND MANUFACTURING METHOD THEREOF, SEMICONDUCTOR PACKAGE, AND ELECTRONIC APPARATUS

SEMICONDUCTOR CHIP WITH THROUGH ELECTRODES AND METHOD FOR MANUFACTURING THE SAME

WAFER LEVEL DIODE PACKAGE STRUCTURE

Wafer level processing method and structure to manufacture semiconductor chip

Manufacturing method of bump structure with annular support

Component having a through-contact

Cu pillar bump with non-metal sidewall spacer and metal top cap

Pad configurations for an electronic package assembly

Semiconductor chip

Semiconductor device with stress relaxation during wire-bonding

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Semiconductor device with grounding conductor film formed on upper surface of dielectric film formed above integrated circuit

Manufacturing method of semiconductor device, and mounting structure thereof

Semiconductor wafer structure and multi-chip stack structure

Semiconductor wafer structure and multi-chip stack structure

Strength of micro-bump joints

Reliable metal bumps on top of I/O pads after removal of test probe marks

Method for Fabricating a Semiconductor Chip Package and Semiconductor Chip Package

Semiconductor device with substrate-side exposed device-side electrode and method of fabrication

Activation treatments in plating processes

Substrate interconnections having different sizes

Integrated circuit and method for fabricating the same

Bump structure and fabrication method thereof

Controlling Solder Bump Profiles by Increasing Heights of Solder Resists

Semiconductor apparatus and semiconductor apparatus unit

Package systems having interposers with interconnection structures

Chip-exposed semiconductor device and its packaging method

Fluorine depleted adhesion layer for metal interconnect structure

WAFER LEVEL PACKAGE AND METHOD OF MANUFACTURING THE SAME

Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Method of fabricating bump structure

WAFER LEVEL INTEGRATION MODULE WITH INTERCONNECTS

Precise-aligned lock-and-key bonding structures

Semiconductor Components Having Conductive Vias With Aligned Back Side Conductors

Semiconductor device for preventing crack in pad region and fabricating method thereof

Semiconductor device and method for fabricating semiconductor device

Die backside standoff structures for semiconductor devices

Hermetic wafer-to-wafer bonding with electrical interconnection

HERMETIC WAFER-TO-WAFER BONDING WITH ELECTRICAL INTERCONNECTION

Gold-tin etch using combination of halogen plasma and wet etch

Isolating wire bonding in integrated electrical components

Electronic elements and devices with trench under bond pad feature

Carbon nanotube circuit component structure

Semiconductor device having trench-isolated element formation region

WAFER LEVEL CHIP SCALE PACKAGE WITH ANNULAR REINFORCEMENT STRUCTURE

MICROELECTRONIC ASSEMBLIES HAVING COMPLIANCY

Cu pillar bump with non-metal sidewall protection structure

Magnetic intermetallic compound interconnect

Method of forming nanoscale three-dimensional patterns in a porous material

Cu pillar bump with electrolytic metal sidewall protection

Semiconductor method of forming bump on substrate to prevent ELK ILD delamination during reflow process

Wafer-bump structure

THROUGH-SUBSTRATE VIA AND FABRICATION METHOD THEREOF

Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods

Method of manufacturing semiconductor apparatus

STACKED WAFER MANUFACTURING METHOD

High speed, high density, low power die interconnect system

High speed, high density, low power die interconnect system

Integrated Circuit Package Having Under-Bump Metallization

Conductive feature for semiconductor substrate and method of manufacture

Routing layer for mitigating stress in a semiconductor die

Method for fabricating bump structure without UBM undercut

Method of forming a micro pin hybrid interconnect array

Method of manufacturing semiconductor device

Wafer-level chip-scale package device having bump assemblies configured to mitigate failures due to stress

Chip package and method for forming the same

Semiconductor package and multichip arrangement having a polymer layer and an encapsulant

Radiate under-bump metallization structure for semiconductor devices

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

LED DIE STRUCTURE AND METHOD FOR MANUFACTURING THE BOTTOM TERMINAL THEREOF

PHOTO-EMISSION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

Semiconductor device, method for manufacturing semiconductor device, apparatus for manufacturing semiconductor device, and method for evaluating semiconductor device

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Method of making semiconductor package having redistribution layer

Chipstack package and manufacturing method thereof

Semiconductor structure and manufacturing method of semiconductor structure

Electronic device package and fabrication method thereof

Through-wafer interconnects for photoimager and memory wafers

Semiconductor device provided with tin diffusion inhibiting layer, and manufacturing method of the same

Semiconductor device and method of forming a dual UBM structure for lead free bump connections

Semiconductor device and method of manufacturing the same

Integrated circuit system with stress redistribution layer and method of manufacture thereof

Cu pillar bump with non-metal sidewall protection structure

Integrated circuit packages

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide

Semiconductor chip package structure for achieving flip-chip type electrical connection without using wire-bonding process and method for making the same

MULTI-CHIP STACK STRUCTURE HAVING THROUGH SILICON VIA

Electronic device having interconnections, openings, and pads having greater width than the openings

Enhanced WLP for superior temp cycling, drop test and high current applications

Die stacking with an annular via having a recessed socket

Method of sensing magnitude of current through semiconductor power device

Semiconductor device and method of forming vertically offset bond on trace interconnects on different height traces

Method of fabricating a semiconductor device that limits damage to elements of the semiconductor device that are exposed during processing

Methods and devices for fabricating and assembling printable semiconductor elements

CONNECTING PAD PRODUCING METHOD

INKS AND PASTES FOR SOLAR CELL FABRICATON

Method for fabricating circuit component

METHOD FOR FORMING A DOUBLE EMBOSSING STRUCTURE

Chip package and method for fabricating the same

Manufacturing method of a bump structure having a reinforcement member

Semiconductor device with copper wirebond sites and methods of making same

SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION AND METHOD OF FORMING SAME

CHIP PACKAGE

Method of manufacturing semiconductor device

Method for forming pad in wafer with three-dimensional stacking structure

Circuit component with conductive layer structure

Wirebondless wafer level package with plated bumps and interconnects

Chip structure

Semiconductor device and penetrating electrode testing method

Light-emitting device, light-emitting element and method of manufacturing same

Method of making a semiconductor device having a conductive particle on an electric pad

Semiconductor device and process for fabricating the same

METAL-EMBEDDED SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE USING THE SAME

Stress-reduced Ni-P/Pd stacks for bondable wafer surfaces

Method of improving adhesion of bond pad over pad metallization with a neighboring passivation layer by depositing a palladium layer

Method of fabricating a conductive post on an electrode

Semiconductor device and method of patterning resin insulation layer on substrate of the same

Semiconductor chip with a bonding pad having contact and test areas

Solder bump structure for flip chip semiconductor devices and method of manufacturing therefore

Semiconductor module, method for fabricating the semiconductor module, and mobile apparatus

Pillar structure having a non-planar surface for semiconductor devices

Electromigration immune through-substrate vias

Method to form solder deposits on substrates

Solder bump interconnect

Package substrate capable of controlling the degree of warpage

Semiconductor Device and Bump Formation Process

Stress buffer structures in a mounting structure of a semiconductor device

T-shaped post for semiconductor devices

GAAS INTEGRATED CIRCUIT DEVICE AND METHOD OF ATTACHING SAME

Semiconductor device and method of manufacturing the same

Semiconductor chip, semiconductor mounting module, mobile communication device, and process for producing semiconductor chip

Polishing solution for CMP, and method for polishing substrate using the polishing solution for CMP

PACKAGING BOARD AND MANUFACTURING METHOD THEREFOR, SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREFOR, AND PORTABLE DEVICE

Semiconductor device and manufacturing method thereof

Semiconductor device having conductive pads and a method of manufacturing the same

METHOD OF FORMING AN EM PROTECTED SEMICONDUCTOR DIE

Method of manufacturing an interconnect structure for a semiconductor device

Method of manufacturing semiconductor device

Method for providing and connecting two contact areas of a semiconductor component or a substrate, and a substrate having two such connected contact areas

Through-silicon via formed with a post passivation interconnect structure

Grid array connection device and method

SEMICONDUCTOR DEVICE

Chip package and fabrication method thereof

Solder Pillars in Flip Chip Assembly

Semiconductor device including a DC-DC converter having a metal plate

Electroless plating of porous and non-porous nickel layers, and gold layer in semiconductor device

Semiconductor device having elastic solder bump to prevent disconnection

Germanium film optical device

Semiconductor Process, Semiconductor Element and Package Having Semiconductor Element

Semiconductor element and package having semiconductor element

Electromigration-resistant under-bump metallization of nickel-iron alloys for Sn-rich solder bumps in Pb-free flip-clip

Micro-bump structure

Semiconductor device and method for manufacturing the same

RELIABLE LARGE DIE FAN-OUT WAFER LEVEL PACKAGE AND METHOD OF MANUFACTURE

Chip package

Method for fabricating electrical bonding pads on a wafer

Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods

Method for manufacturing chips

METALLIZATION LAYER STRUCTURE FOR FLIP CHIP PACKAGE

Semiconductor device and method for fabricating the same

Structures and methods to reduce maximum current density in a solder ball

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

METHOD OF VERTICALLY MOUNTING AN INTEGRATED CIRCUIT

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor processing methods

Packaging conductive structure and method for manufacturing the same

Semiconductor connection component

Semiconductor device and manufacturing method thereof

Reverse side engineered III-nitride devices

Bonding structure and method for manufacturing same

Method for manufacturing a semiconductor apparatus having a through-hole interconnection

Methods of forming conductive vias

Conductor bump method and apparatus

Semiconductor Wafer and Method of Manufacturing the Same and Method of Manufacturing Semiconductor Device

Through-silicon via with air gap

Microelectronic devices including conductive vias, conductive caps and variable thickness insulating layers

Multi-chip stacked package and its mother chip to save interposer

Pressure-bonded ball diameter detecting apparatus and pressure-bonded ball diameter detecting method

Solder structure, method for forming the solder structure, and semiconductor module including the solder structure

Semiconductor Device and Method of Forming Bump Structure with Multi-Layer UBM Around Bump Formation Area

Semiconductor device and method for making the same

Semiconductor chip and semiconductor package including the same

Manufacturing method of semiconductor integrated circuit device

Semiconductor device and method of manufacturing same

Bumping free flip chip process

Pad structure for semiconductor devices

Method for creating highly compliant thermal bonds that withstand relative motion of two surfaces during temperature changes using spacing structures

Bonding apparatus and bonding method

Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer

Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods

Via structures and semiconductor devices having the via structures

Integrated Circuit

Semiconductor component having through wire interconnect with compressed bump

Wafer level chip scale package and process of manufacture

Pad structure with a nano-structured coating film

Semiconductor devices having redistribution structures and packages, and methods of forming the same

Integrated circuit packaging system with core region and bond pad and method of manufacture thereof

Semiconductor device including bottom surface wiring and manfacturing method of the semiconductor device

Semiconductor die contact structure and method

Semiconductor device and method of forming column interconnect structure to reduce wafer stress

Crack resistant circuit under pad structure and method of manufacturing the same

Via forming method and method of manufacturing multi-chip package using the same

Semiconductor chip, wafer stack package using the same, and methods of manufacturing the same

Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument

Methods for fabricating and filling conductive vias and conductive vias so formed

Small area, robust silicon via structure and process

Electronic component, semiconductor device, methods of manufacturing the same, circuit board, and electronic instrument

LEADLESS SEMICONDUCTOR DEVICE TERMINAL

Routing layer for mitigating stress in a semiconductor die

High voltage resistance coupling structure

Preventing UBM oxidation in bump formation processes

Stacked semiconductor package and method for manufacturing the same

Semiconductor device fabrication method including formation of columnar electrodes having protrusion sections

Method for manufacturing and testing an integrated electronic circuit

Terminal structure, electronic device, and manufacturing method thereof

METALLIC BUMP STRUCTURE WITHOUT UNDER BUMP METALLURGY AND A MANUFACTURING METHOD THEREOF

ASSEMBLY OF SEMICONDUCTOR CHIPS/WAFERS

SYSTEM AND METHOD FOR PREVENTING METAL CORROSION ON BOND PADS

Pad bonding employing a self-aligned plated liner for adhesion enhancement

Electronic structures including conductive layers comprising copper and having a thickness of at least 0.5 micrometers

Reducing Device Mismatch by Adjusting Titanium Formation

Semiconductor device and information processing system including the same

METAL WIRING STRUCTURE COMPRISING ELECTROLESS NICKEL PLATING LAYER AND METHOD OF FABRICATING THE SAME

Manufacturing method for semiconductor devices

Integrated circuit with protective structure

Semiconductor device having a copper plug

Chip package and fabrication method thereof

Integrated circuit chip and flip chip package having the integrated circuit chip

Chip package and fabrication method thereof

Semiconductor device

Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die

Method for manufacturing a semiconductor component

Semiconductor device with copper wire having different width portions

Semiconductor device and method of manufacturing the same

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Semiconductor device and method for manufacturing same

Template and pattern forming method

Method of manufacturing semiconductor device

Wafer backside interconnect structure connected to TSVs

METHOD OF BONDING PARTS TO SUBSTRATE USING SOLDER PASTE

Process for producing a contact area of an electronic component

Wafer level integration module with interconnects

Protection layer for preventing UBM layer from chemical attack and oxidation

Method of integrating a MOSFET with a capacitor

Die Package

Enhanced copper posts for wafer level chip scale packaging

Semiconductor Chip with Stair Arrangement Bump Structures

Metal-oxide-semiconductor chip and fabrication method thereof

Solder joint reliability in microelectronic packaging

Using interrupted through-silicon-vias in integrated circuits adapted for stacking

Semiconductor chip with contoured solder structure opening

Methods and structures for controlling wafer curvature

Self-aligned protection layer for copper post structure

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

Method of manufacturing wafer level device package

BONDING STRUCTURES AND METHODS OF FORMING BONDING STRUCTURES

Semiconductor apparatus and fabrication method thereof

Semiconductor device having stable signal transmission at high speed and high frequency

Chip package with heavily doped region and fabrication method thereof

Chip package with heavily doped regions and fabrication method thereof

Method For Fabricating A Through Interconnect On A Semiconductor Substrate

Chip package and fabrication method thereof