Electrical connection structure

Interconnection element with posts formed by plating

3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach

Package structure and substrate bonding method

Through silicon via with embedded barrier pad

Glass frit wafer bond protective structure

Semiconductor module with a semiconductor chip and a passive component and method for producing the same

Semiconductor structure with low-melting-temperature conductive regions, and method of repairing a semiconductor structure

Semiconductor device

Through-silicon via resonators in chip packages and methods of assembling same

Connection structure, wiring substrate unit, electronic circuit part unit, and electronic apparatus

Method for chip packaging

Semiconductor device fabrication method capable of scribing chips with high yield

Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device

Electronic component implementing structure intermediate body, electronic component implementing structure body and manufacturing method of electronic component implementing structure body

Chip pad resistant to antenna effect and method

Methods and apparatus for solder connections

Method and structure of sensors and MEMS devices using vertical mounting with interconnections

Pad structure of a semiconductor device, method of manufacturing the pad structure and semiconductor package including the pad structure

Cleaning methods and compositions

Method to realize flux free indium bumping

Apparatus and method for integration of through substrate vias

Semiconductor device packages and methods

SYSTEM AND METHODS FOR WIRE BONDING

Package on package structures and methods for forming the same

Strain reduced structure for IC packaging

Device with pillar-shaped components

Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same

Method for designing a package and substrate layout

Process for direct bonding two elements comprising copper portions and portions of dielectric materials

Semiconductor structures and methods of manufacture

Electronic components assembly

SEMICONDUCTOR DEVICE AND METHOD OF ASSEMBLING SAME

Integrated circuit and method of manufacturing the same

Methods and apparatus of wafer level package for heterogeneous integration technology

Method of fabricating semiconductor device using gang bonding and semiconductor device fabricated by the same

Fluxing-encapsulant material for microelectronic packages assembled via thermal compression bonding process

Bottom-up plating of through-substrate vias

3-D Integrated Circuits and Methods of Forming Thereof

Tree based adaptive die enumeration

Package on package structures and methods for forming the same

3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias

Bonded processed semiconductor structures and carriers

Semiconductor device and manufacturing method for the same

Semiconductor device

STACKED SEMICONDUCTOR COMPONENTS WITH UNIVERSAL INTERCONNECT FOOTPRINT

Bonding pad structure with dense via array

Shallow via formation by oxidation

Semiconductor device

Semiconductor device

Semiconductor package

Semiconductor package

Elongated bumps in integrated circuit devices

SEMICONDUCTOR CHIP DEVICE WITH FRAGMENTED SOLDER STRUCTURE PADS

Packaging device and method of making the same

Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die

Multichip power semiconductor device

Chip arrangement, a method for forming a chip arrangement, a chip package, a method for forming a chip package

Polymer via plugs with high thermal integrity

Electromigration-resistant lead-free solder interconnect structures

Method of manufacturing a semiconductor integrated circuit device

Direct bonding process using a compressible porous layer

Magnet assisted alignment method for wafer bonding and wafer level chip scale packaging

Semiconductor device and method of forming micro-vias partially through insulating material over bump interconnect conductive layer for stress relief

Conductive bump structure on substrate and fabrication method thereof

Method for manufacturing fine-pitch bumps and structure thereof

Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation

ELECTROMIGRATION-RESISTANT LEAD-FREE SOLDER INTERCONNECT STRUCTURES

Solid-state device including a conductive bump connected to a metal pattern and method of manufacturing the same

Semiconductor device and method of simultaneous testing of multiple interconnects for electro-migration

Method of manufacturing a semiconductor component

Integrated circuit chip using top post-passivation technology and bottom structure technology

Semiconductor device

Joint structure for substrates and methods of forming

Semiconductor device and method of forming interposer and opposing build-up interconnect structure with connecting conductive TMV for electrical interconnect of FO-WLCSP

Semiconductor structure and method of forming the same

Integrated antennas in wafer level package

Wire Bonding Structures for Integrated Circuits

Stack semiconductor apparatus having a through silicon via and method of fabricating the same

Methods and apparatus for solder on slot connections in package on package structures

Methods and apparatus of guard rings for wafer-level-packaging

Electronic system having increased coupling by using horizontal and vertical communication channels

Eutectic bonding of thin chips on a carrier substrate

Contact test structure and method

Semiconductor device bonding with stress relief connection pads

Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration

Semiconductor constructions

Self-aligned polymer passivation/aluminum pad

Structures and methods for detecting solder wetting of pedestal sidewalls

Semiconductor component that includes a protective structure

Semiconductor device including a stress buffer material formed above a low-k metallization system

Silicon carbide semiconductor device and manufacturing method thereof

Surface metal wiring structure for an IC substrate

Protection layers for conductive pads and methods of formation thereof

Copper interconnects having a titanium-platinum-titanium assembly between copper and compound semiconductor

Semiconductor device and method of forming protective coating over interconnect structure to inhibit surface oxidation

Method for manufacturing semiconductor devices having a glass substrate

Electrical connections for chip scale packaging

Method for chip package

Magnetic attachment structure

Devices and methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure

Mechanisms for forming connectors with a molding compound for package on package

Semiconductor device and method of manufacturing semiconductor device

Power semiconductor module

Devices and methods related to interconnect conductors to reduce de-lamination

Double-sided vertical semiconductor device with thinned substrate

Methods of stripping resist after metal deposition

Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die

Bumping process and structure thereof

Semiconductor devices having conductive via structures and methods for fabricating the same

Big via structure

Semiconductor device, method for manufacturing semiconductor device, and electronic apparatus

Chip assembly system

Semiconductor device and method for manufacturing the same

Method of manufacturing a semiconductor device and wafer

Post-passivation interconnect structure AMD method of forming same

Semiconductor chip comprising a plurality of contact pads and a plurality of associated pad cells

Method of manufacturing a semiconductor device

Semiconductor devices having through-vias and methods for fabricating the same

Semiconductor devices having through-vias and methods for fabricating the same

Interconnect crack arrestor structure and methods

Biosensor chip and a method of manufacturing the same

Semiconductor device using diffusion soldering

Via connection structures, semiconductor devices having the same, and methods of fabricating the structures and devices

Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same

Semiconductor packages and methods of manufacturing the same

ELECTROMAGNETIC FIELD ASSISTED SELF-ASSEMBLY WITH FORMATION OF ELECTRICAL CONTACTS

Transfer substrate for forming metal wiring and method for forming metal wiring using said transfer substrate

Method for building vertical pillar interconnect

Bump structural designs to minimize package defects

SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE

Encapsulant with corrosion inhibitor

OPTIMIZATION OF COPPER PLATING THROUGH WAFER VIA

BUMPING PROCESS AND STRUCTURE THEREOF

Integrated Circuit Die And Method Of Fabricating

Semiconductor device

Method for forming pad in wafer with three-dimensional stacking structure

Multi-layer polymer lens and method of making same

Semiconductor device structures and electronic devices including hybrid conductive vias, and methods of fabrication

Carrier, semiconductor package and fabrication method thereof

Crack stopper on under-bump metallization layer

Semiconductor device and method of manufacturing the same

Multi-chip fan out package and methods of forming the same

Package assembly and method of forming the same

Semiconductor packaging structure and method

Sawing underfill in packaging processes

Backside integration of RF filters for RF front end modules and design structure

Biosensor capacitor

BUMPING PROCESS

Bump pad structure

Semiconductor package structure and method for manufacturing the same

Semiconductor devices with compliant interconnects

Package on package interconnect structure

Method of processing a contact pad

Integrated circuit constructions having through substrate vias and methods of forming integrated circuit constructions having through substrate vias

Power semiconductor device with reduced contact resistance

Bonding pad and method of making same

UBM formation for integrated circuits

Semiconductor device and method for manufacturing the same

Stackable semiconductor package and manufacturing method thereof

PACKAGE METHOD FOR ELECTRONIC COMPONENTS BY THIN SUBSTRATE

Electronic-component mounted body, electronic component, and circuit board

Integrated circuit device

Semiconductor package with package on package structure

Method for manufacturing an electronic device by reducing thickness of electronic members attached to a carrier

Chip-on-lead package and method of forming

Semiconductor device having a through-substrate via

ESD protection device

SEMICONDUCTOR DEVICE

Semiconductor wafer plating bus

Quantum Efficiency Back Side Illuminated CMOS Image Sensor And Package, And Method Of Making Same

Integrated compact MEMS device with deep trench contacts

Electronic component and electronic device

SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME

Semiconductor device and method of forming insulating layer in notches around conductive TSV for stress relief

Semiconductor device and method of manufacturing the same

Techniques for wafer-level processing of QFN packages

3D IC configuration with contactless communication

Module including a discrete device mounted on a DCB substrate

Manufacturing method of semiconductor device, processing method of semiconductor wafer, semiconductor wafer

Semiconductor package including stacked semiconductor chips and a redistribution layer

Electronics device package and fabrication method thereof

Microspring structures adapted for target device cooling

Method for packaging semiconductors at a wafer level

Semiconductor Device and Fabrication Method

SEMICONDUCTOR DEVICE INCLUDING THROUGH ELECTRODE AND METHOD OF MANUFACTURING THE SAME AND STACKED PACKAGE INCLUDING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Integrated circuit packaging system with coupling features and method of manufacture thereof

PAD OVER INTERCONNECT PAD STRUCTURE DESIGN

Leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect

SEMICONDUCTOR STACK PACKAGES AND METHODS OF FABRICATING THE SAME

Electrically bonded arrays of transfer printed active components

Treatment, before the bonding of a mixed Cu-oxide surface, by a plasma containing nitrogen and hydrogen

Method of manufacturing bump

Semiconductor device having a chip mounting portion on which a separated plated layer is disposed

Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer

Offset of contact opening for copper pillars in flip chip packages

Semiconductor structure having no adjacent bumps between two adjacent pads

Bump structure design for stress reduction

Post-passivation interconnect structure

Semiconductor device with bump structure on an interconncet structure

Receiver module and device

Device including two power semiconductor chips and manufacturing thereof

Method for forming a reliable solderable contact

Method of processing solder bump by vacuum annealing

Packaging process tools and systems, and packaging methods for semiconductor devices

UBM structures for wafer level chip scale packaging

Circuit connector apparatus and method therefor

Solderable contact and passivation for semiconductor dies

Electrode connecting structures containing copper

Flip chip package utilizing trace bump trace interconnection

Semiconductor device and method of forming patterned repassivation openings between RDL and UBM to reduce adverse effects of electro-migration

TSV structures and methods for forming the same

Electronic device with multi-layer contact

COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT WITH THREE-DIMENSIONALLY FORMED COMPONENTS

Power semiconductor package with conductive clip

Semiconductor devices including protected barrier layers

Flip chip package for DRAM with two underfill materials

Semiconductor device having shielded conductive vias

Semiconductor device and method of forming a power MOSFET with interconnect structure to achieve lower RDSON

Method of fabricating a wafer level semiconductor package having a pre-formed dielectric layer

Package-on-package (PoP) structure including stud bulbs and method

Semiconductor device having wiring pad and wiring formed on the same wiring layer

Semiconductor device and method of forming RDL under bump for electrical connection to enclosed bump

Electrical connection structure

Wafer level chip scale package

Metallization structure for high power microelectronic devices

Method for packaging ultra-thin chip with solder ball thermo-compression in wafer level packaging process

Under bump passive components in wafer level packaging

Methods and apparatus of under bump metallization in packaging semiconductor devices

Device having electrodes formed from bumps with different diameters

Conductive structure and method for forming the same

Mechanisms for forming fine-pitch copper bump structures

Method for developing a custom device

Microelectronic package and method of manufacturing same

Metal pad structure for thickness enhancement of polymer used in electrical interconnection of semiconductor die to semiconductor chip package substrate with solder bump

Bumps for Chip Scale Packaging

Through-silicon via with low-K dielectric liner

Termination structure for gallium nitride schottky diode

Vertical gallium nitride Schottky diode

Method for separating a plurality of dies and a processing device for separating a plurality of dies

Semiconductor structure having lateral through silicon via

Semiconductor device

Semiconductor structure and manufacturing method thereof

Methods of and semiconductor devices with ball strength improvement

Semiconductor device

Post-passivation interconnect structure and method of forming the same

Pad design for circuit under pad in semiconductor devices

Semiconductor device and method of forming interposer frame over semiconductor die to provide vertical interconnect

Method of fabricating land grid array semiconductor package

Flattened substrate surface for substrate bonding

Electronic device and method for fabricating an electronic device

TSV backside processing using copper damascene interconnect technology

Semiconductor device and method of forming thermal interface material and heat spreader over semiconductor die

Laminated semiconductor substrate, semiconductor substrate, laminated chip package and method of manufacturing the same

Microelectronic package with stacked microelectronic units and method for manufacture thereof

Semiconductor device and method

WAFER LEVEL CHIP SCALE PACKAGE DEVICE AND MANUFACTURING METHOD THEROF

Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die

Methods of forming bump structures that include a protection layer

SEMICONDUCTOR PACKAGE HAVING SOLDER JOINTED REGION WITH CONTROLLED AG CONTENT

SEMICONDUCTOR PACKAGE AND STACKED SEMICONDUCTOR PACKAGE

ESD protection device

Bond pad structure and fabricating method thereof

Semiconductor device and method of forming conductive pillar having an expanded base

SEMICONDUCTOR APPARATUS

Through substrate via structures and methods of forming the same

Three-dimensional vertically interconnected structure

Connector structures of integrated circuits

Post-passivation interconnect structure

Semiconductor device

Method of fabricating backside-illuminated image sensor

Packaging process tools and packaging methods for semiconductor devices

Semiconductor structure and method for making same

Integrated circuit structure having dies with connectors of different sizes

Semiconductor package having an anti-contact layer

Methods of packaging semiconductor devices and structures thereof

Copper Stud Bump Wafer Level Package

Wafer level chip scale package and method of manufacturing the same

Semiconductor device having multiple bump heights and multiple bump diameters

Semiconductor device having improved contact structure

Bump with protection structure

Semiconductor device and method of forming prefabricated multi-die leadframe for electrical interconnect of stacked semiconductor die

Electrical connection for chip scale packaging

ELECTRONIC PACKAGING CONNECTOR AND METHODS FOR ITS PRODUCTION

Power management applications of interconnect substrates

Stub minimization for assemblies without wirebonds to package substrate

Electrical device with protruding contact elements and overhang regions over a cavity

Stub minimization for assemblies without wirebonds to package substrate

ELECTRONIC ASSEMBLY HAVING MIXED INTERFACE INCLUDING TSV DIE

SEMICONDUCTOR DEVICE

Stub minimization for assemblies without wirebonds to package substrate

Device having wirelessly enabled functional blocks

Seal ring structure with a metal pad

METHODS OF FORMING CONNECTION BUMP OF SEMICONDUCTOR DEVICE

METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

Bond pad structure

INTEGRATED CIRCUIT AND METHOD OF MAKING

Semiconductor device

Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF