208271 ⎘
Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor; Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed; Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices; Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
Sub-classes:METHOD FOR MAKING GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLATTICE
#2MEMORY DEVICE INCLUDING A SUPERLATTICE GETTERING LAYER
#3Method for making memory device including a superlattice gettering layer
#4METHOD FOR MAKING SEMICONDUCTOR DEVICE INCLUDING SUPERLATTICE WITH OXYGEN AND CARBON MONOLAYERS
#5SEMICONDUCTOR STRUCTURES WITH MULTIPLE THRESHOLD VOLTAGE OFFERINGS AND METHODS THEREOF
#6Quantum Dipole Battery
#7METHODS FOR MAKING BIPOLAR JUNCTION TRANSISTORS INCLUDING EMITTER-BASE AND BASE-COLLECTOR SUPERLATTICES
#8GATE-ALL-AROUND (GAA) DEVICE INCLUDING A SUPERLATTICE
#9Semiconductor device including a superlattice and an asymmetric channel and related methods
#10BIPOLAR JUNCTION TRANSISTORS INCLUDING EMITTER-BASE AND BASE-COLLECTOR SUPERLATTICES
#11Method for making semiconductor device including superlattice with oxygen and carbon monolayers
#12Semiconductor device, method of manufacturing the same and electronic device including the device
#13Semiconductor device including superlattice with O18 enriched monolayers
#14SEMICONDUCTOR DEVICE WITH HIGH-ELECTRON MOBILITY TRANSISTOR
#15Method for making gate-all-around (GAA) device including a superlattice
#16Gate-all-around (GAA) device including a superlattice
#17Method for making semiconductor device including superlattice with O18 enriched monolayers
#18Semiconductor device including superlattice with Oenriched monolayers
#19Bipolar junction transistors including emitter-base and base-collector superlattices
#20Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
#21Enhanced cascade field effect transistor
#22Semiconductor structures with multiple threshold voltage offerings and methods thereof
#23Vertical semiconductor device with enhanced contact structure and associated methods
#24Steep sloped vertical tunnel field-effect transistor
#25Semiconductor device including a superlattice and an asymmetric channel and related methods
#26Semiconductor device including capacitor
#27Method for making semiconductor device including superlattice with oxygen and carbon monolayers
#28Semiconductor device including superlattice with oxygen and carbon monolayers
#29Semiconductor device including a superlattice and providing reduced gate leakage
#30Semiconductor device including capacitor
#31Semiconductor device including a superlattice with different non-semiconductor material monolayers
#32Bipolar junction transistors including emitter-base and base-collector superlattices
#33Methods for making bipolar junction transistors including emitter-base and base-collector superlattices
#34Superlattice films for photonic and electronic devices
#35THIN FILM TRANSISTOR
#36Vertical semiconductor device with enhanced contact structure and associated methods
#37Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices
#38Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods
#39Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice
#40Semiconductor device including capacitor
#41Quantum dot devices with selectors
#42Semiconductor device including a superlattice and an asymmetric channel and related methods
#43Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods
#44Semiconductor device, method of manufacturing the same and electronic device including the device
#45Creating arbitrary patterns on a 2-d uniform grid VCSEL array
#46COMPOUND SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR COMPOUND SEMICONDUCTOR DEVICE, AND AMPLIFIER
#47Steep sloped vertical tunnel field-effect transistor
#48Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
#49Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
#50Method for making a FINFET having reduced contact resistance
#51Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods
#52METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE HAVING NITROGEN DIFFUSED THEREIN
#53Semiconductor device including superlattice structures with reduced defect densities
#54Semiconductor device, method of manufacturing the same, and electronic device including the device
#55Enhanced cascade field effect transistor
#56Quantum dot devices with modulation doped stacks
#57Creating arbitrary patterns on a 2-D uniform grid VCSEL array
#58Steep sloped vertical tunnel field-effect transistor
#59Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice
#60Inverted T channel field effect transistor (ITFET) including a superlattice
#61Method for making an inverted T channel field effect transistor (ITFET) including a superlattice
#62Semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice
#63IC unit and method of manufacturing the same, and electronic device including the same
#64Semiconductor device including enhanced contact structures having a superlattice
#65Semiconductor device including stressed source/drain, method of manufacturing the same and electronic device including the same
#66Method for making a semiconductor device including enhanced contact structures having a superlattice
#67Method for making CMOS image sensor including pixels with read circuitry having a superlattice
#68CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
#69CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
#70CMOS image sensor including pixels with read circuitry having a superlattice
#71Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice
#72Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice
#73GATE PATTERNING FOR QUANTUM DOT DEVICES
#74Layer, multilevel element, method for fabricating multilevel element, and method for driving multilevel element
#75Layer, multilevel element, method for fabricating multilevel element, and method for driving multilevel element
#76Optoelectronic semiconductor chip
#77Creating arbitrary patterns on a 2-D uniform grid VCSEL array
#78Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface
#79Semiconductor device
#80Semiconductor device with recessed channel array transistor (RCAT) including a superlattice
#81Method for making DRAM with recessed channel array transistor (RCAT) including a superlattice
#82Vertical channel devices and method of fabricating same
#83Method of forming vertical channel devices
#84Method of fabricating vertical transistor device
#85III-N based substrate for power electronic devices and method for manufacturing same
#86Heterostructures and electronic devices derived therefrom
#87IC unit and methond of manufacturing the same, and electronic device including the same
#88Semiconductor device, method of manufacturing the same and electronic device including the same
#89Semiconductor device, method of manufacturing the same and electronic device including the device
#90Optoelectronic semiconductor chip
#91Method for making a semiconductor device including threshold voltage measurement circuitry
#92Semiconductor device including threshold voltage measurement circuitry
#93Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers
#94Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice
#95Semiconductor device including resonant tunneling diode structure having a superlattice
#96Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers
#97Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods
#98Semiconductor quantum dot device and method for forming a scalable linear array of quantum dots
#99Semiconductor devices with enhanced deterministic doping and related methods
#100Superlattice lateral bipolar junction transistor
#101Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains
#102Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
#103Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
#104Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
#105Nitride semiconductor device, production method thereof, diode, and field effect transistor
#106Semiconductor device including a superlattice and replacement metal gate structure and related methods
#107Vertical semiconductor devices including superlattice punch through stop layer and related methods
#108Nitride semiconductor structure
#109Nano-structure assembly and nano-device comprising same
#110Semiconductor devices with enhanced deterministic doping and related methods
#111Bipolar transistor
#112Direct tunnel barrier control gates in a two-dimensional electronic system
#113Epitaxial wafer for heterojunction type field effect transistor
#114Schottky diode
#115Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains
#116Low thermal conductivity material
#117Method of forming quantum well mosfet channels having uni-axial strains caused by metal source/drains
#118NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
#119Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains
#120LAMINATED STRUCTURES
#121ELECTRONIC DEVICE INCLUDING AN ELECTRICALLY POLLED SUPERLATTICE AND RELATED METHODS
#122Incorporating gate control over a resonant tunneling structure in CMOS to reduce off-state current leakage, supply voltage and power consumption
#123Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains
#124Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains
#125Schottky barrier quantum well resonant tunneling transistor
#126Semiconductor device method of manfacturing a quantum well structure and a semiconductor device comprising such a quantum well structure
#127INSULATING FILM AND ELECTRONIC DEVICE
#128Insulating film and electronic device
#129INSULATING FILM AND ELECTRONIC DEVICE
#130INSULATING FILM AND ELECTRONIC DEVICE
#131Method for making a semiconductor device comprising a lattice matching layer
#132Semiconductor device comprising a lattice matching layer
#133ELECTRONIC DEVICE INCLUDING A SELECTIVELY POLABLE SUPERLATTICE
#134METHOD FOR MAKING AN ELECTRONIC DEVICE INCLUDING A SELECTIVELY POLABLE SUPERLATTICE
#135ELECTRONIC DEVICE INCLUDING A POLED SUPERLATTICE HAVING A NET ELECTRICAL DIPOLE MOMENT
#136Coupled quantum well devices (CQWD) containing two or more direct selective contacts and methods of making same
#137Semiconductor device including a front side strained superlattice layer and a back side stress layer
#138Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
#139Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions
#140Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
#141Semiconductor device including a strained superlattice and overlying stress layer and related methods
#142Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
#143Semiconductor Device Including a Channel with a Non-Semiconductor Layer Monolayer
#144Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
#145Semiconductor device including a strained superlattice layer above a stress layer
#146Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
#147Method for Making a FINFET Including a Superlattice
#148Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor Layer
#149METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A DOPANT BLOCKING SUPERLATTICE
#150Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
#151METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A MEMORY CELL WITH A NEGATIVE DIFFERENTIAL RESISTANCE (NDR) DEVICE
#152Method for Making a Microelectromechanical Systems (MEMS) Device Including a Superlattice
#153Semiconductor device including a memory cell with a negative differential resistance (NDR) device
#154Semiconductor device method of manufacturing a quantum well structure and a semiconductor device comprising such a quantum well structure
#155Insulating film and electronic device
#156Insulating film and electronic device
#157Insulating film and electronic device
#158Method for making a semiconductor device comprising a superlattice dielectric interface layer
#159Semiconductor device comprising a superlattice dielectric interface layer
#160Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layers
#161Semiconductor device including a superlattice having at least one group of substantially undoped layers
#162Method for making a semiconductor device including band-engineered superlattice using intermediate annealing
#163Semiconductor device including MOSFET having band-engineered superlattice
#164Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
#165Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel
#166Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
#167Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
#168Semiconductor device including a superlattice with regions defining a semiconductor junction
#169Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
#170Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions
#171Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions
#172Electronic device and method of fabricating the same
#173Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
#174Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
#175Semiconductor device comprising a superlattice channel vertically stepped above source and drain regions
#176Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structure
#177Insulating film and electronic device
#178Method for making an integrated circuit comprising a waveguide having an energy band engineered superlattice
#179Method for making an integrated circuit comprising an active optical device having an energy band engineered superlattice
#180Integrated circuit comprising a waveguide having an energy band engineered superlattice
#181Integrated circuit comprising an active optical device having an energy band engineered superlattice
#182Method for making electronic device comprising active optical devices with an energy band engineered superlattice
#183Electronic device comprising active optical devices with an energy band engineered superlattice
#184Semiconductor device including band-engineered superlattice
#185Method for making a varactor with hyper-abrupt junction region including a superlattice
#186Varactor with hyper-abrupt junction region including spaced-apart superlattices
#187Method for making a semiconductor device having reduced contact resistance
#188FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance
#189Creating arbitrary patterns on a 2-D uniform grid VCSEL array
#190Multiple layer quantum well FET with a side-gate
#191Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts