Santa Clara, California
United States
123
2025-08-14
The entities that hold a legal rights for patent applications filed by inventor Kai James:
James Kai from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:
HIGH BANDWIDTH NON-VOLATILE MEMORY
#2 | 2025-04-17THREE-DIMENSIONAL MEMORY DEVICE INCLUDING SLOPING WORD LINES FOR STAIRLESS CONTACT AND METHODS OF FORMING THE SAME
#3 | 2024-08-29THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTI-LEVEL WORD LINE CONTACT WELLS AND METHODS FOR MANUFACTURING THE SAME
#4 | 2024-05-23THREE-DIMENSIONAL MEMORY DEVICE WITH SEPARATED SOURCE LINES AND METHOD OF MAKING THE SAME
#5 | 2024-05-09THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTI-LEVEL SUPPORT BRIDGE STRUCTURES AND METHODS FOR FORMING THE SAME
#6 | 2024-04-18THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LATERALLY SEPARATED SOURCE LINES AND METHOD OF MAKING THE SAME
#7 | 2024-02-15Dynamic word line reconfiguration for NAND structure
#8 | 2023-05-25Bonded semiconductor die assembly containing through-stack via structures and methods for making the same
#9 | 2023-02-09Three-dimensional memory device with separated contact regions and methods for forming the same
#10 | 2022-07-21Non-volatile memory with memory array between circuits
#11 | 2022-01-27Bonded semiconductor die assembly containing through-stack via structures and methods for making the same
#12 | 2021-11-18Three-dimensional memory device with wiggled drain-select-level isolation structure and methods of manufacturing the same
#13 | 2021-10-28Three-dimensional memory device employing thinned insulating layers and methods for forming the same
#14 | 2021-10-28Three-dimensional memory device employing thinned insulating layers and methods for forming the same
#15 | 2021-07-08THREE-DIMENSIONAL MEMORY DEVICE WITH DIELECTRIC ISOLATED VIA STRUCTURES AND METHODS OF MAKING THE SAME
#16 | 2021-02-18Three-dimensional memory device containing alternating stack of source layers and drain layers and vertical gate electrodes
#17 | 2021-02-18Three-dimensional memory device containing alternating stack of source layers and drain layers and vertical gate electrodes
#18 | 2021-02-04Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
#19 | 2021-01-28Three-dimensional memory device including self-aligned dielectric isolation regions for connection via structures and method of making the same
#20 | 2021-01-07Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same
#21 | 2020-11-12Method for removing a bulk substrate from a bonded assembly of wafers
#22 | 2020-09-10Three-dimensional device with bonded structures including a support die and methods of making the same
#23 | 2020-08-13Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
#24 | 2020-08-13Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
#25 | 2020-08-13Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
#26 | 2020-08-06Three-dimensional memory device with drain-select-level isolation structures and method of making the same
#27 | 2020-08-06Three-dimensional memory device with drain-select-level isolation structures and method of making the same
#28 | 2020-07-28Method for removing a bulk substrate from a bonded assembly of wafers
#29 | 2020-07-23Through-array conductive via structures for a three-dimensional memory device and methods of making the same
#30 | 2020-07-23Three-dimensional memory device containing bond pad-based power supply network for a source line and methods of making the same
#31 | 2020-06-16Three-dimensional memory device with drain-select-level isolation structures and method of making the same
#32 | 2020-06-16Three-dimensional memory device with drain-select-level isolation structures and method of making the same
#33 | 2020-04-21Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
#34 | 2020-03-05Three dimensional ferroelectric memory
#35 | 2020-01-09Non-volatile memory with pool capacitor
#36 | 2020-01-09Non-volatile memory with pool capacitor
#37 | 2019-12-05THREE-DIMENSIONAL MEMORY DEVICE WITH SEMICIRCULAR METAL-SEMICONDUCTOR ALLOY FLOATING GATE ELECTRODES AND METHODS OF MAKING THEREOF
#38 | 2019-09-12Three-dimensional memory device and method of making the same using concurrent formation of memory openings and contact openings
#39 | 2019-09-12Concurrent formation of memory openings and contact openings for a three-dimensional memory device
#40 | 2019-08-29Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same
#41 | 2019-07-25Three-dimensional memory device including contact via structures that extend through word lines and method of making the same
#42 | 2019-07-18Three-dimensional flat inverse NAND memory device and method of making the same
#43 | 2019-07-16Concurrent formation of memory openings and contact openings for a three-dimensional memory device
#44 | 2019-05-14Three-dimensional memory device containing floating gate select transistor
#45 | 2019-01-24Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same
#46 | 2019-01-24Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same
#47 | 2018-12-06Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof
#48 | 2018-09-13Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
#49 | 2018-08-30High voltage field effect transistor with laterally extended gate dielectric and method of making thereof
#50 | 2018-08-23Grouping memory cells into sub-blocks for program speed uniformity
#51 | 2018-08-16Three-dimensional NAND memory device with common bit line for multiple NAND strings in each memory block
#52 | 2018-07-26Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof
#53 | 2018-05-31Three-dimensional array device having a metal containing barrier and method of making thereof
#54 | 2018-05-17Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof
#55 | 2018-05-03Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
#56 | 2018-05-03Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
#57 | 2018-05-03Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
#58 | 2018-05-01Grouping memory cells into sub-blocks for program speed uniformity
#59 | 2018-04-24Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof
#60 | 2018-04-05Three-dimensional memory device having drain select level isolation structure and method of making thereof
#61 | 2018-03-20Three-dimensional memory device containing separately formed drain select transistors and method of making thereof
#62 | 2018-02-08Three-dimensional memory device with semicircular metal-semiconductor alloy floating gate electrodes and methods of making thereof
#63 | 2017-12-21Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof
#64 | 2017-11-21Three-dimensional memory device containing a lateral source contact and method of making the same
#65 | 2017-10-31Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making and using thereof
#66 | 2017-06-22Through-memory-level via structures for a three-dimensional memory device
#67 | 2017-06-22Through-memory-level via structures for a three-dimensional memory device
#68 | 2017-06-22Through-memory-level via structures for a three-dimensional memory device
#69 | 2017-05-25Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same
#70 | 2017-05-25Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same
#71 | 2017-05-25Within array replacement openings for a three-dimensional memory device
#72 | 2016-11-22Multi tier three-dimensional memory devices including vertically shared bit lines
#73 | 2016-08-18Non-volatile storage element with suspended charge storage region
#74 | 2016-03-24Monolithic three-dimensional NAND strings and methods of fabrication thereof
#75 | 2015-12-24Three dimensional vertical NAND device with floating gates
#76 | 2015-10-15Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks
#77 | 2015-07-30Non-volatile storage element with suspended charge storage region
#78 | 2015-05-21NAND string containing self-aligned control gate sidewall cladding
#79 | 2015-05-07Non-volatile memory with flat cell structures and air gap isolation
#80 | 2015-03-12Three dimensional NAND device with silicide containing floating gates and method of making thereof
#81 | 2015-01-01NAND string containing self-aligned control gate sidewall cladding
#82 | 2014-12-18Method of forming an active area with floating gate negative offset profile in FG NAND memory
#83 | 2014-11-27Memory device with control gate oxygen diffusion control and method of making thereof
#84 | 2014-11-27Inverted-T word line and formation for non-volatile storage
#85 | 2014-06-26Three dimensional NAND device with silicide containing floating gates
#86 | 2014-06-05Select gate formation for nanodot flat cell
#87 | 2014-01-02Non-volatile memory structure containing nanodots and continuous metal layer charge traps and method of making thereof
#88 | 2014-01-02NAND memory device containing nanodots and method of making thereof
#89 | 2013-03-21Ultrahigh density vertical NAND memory device and method of making thereof
#90 | 2012-08-09Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof
#91 | 2012-06-21Stacked metal fin cell
#92 | 2012-06-05Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution
#93 | 2012-03-29Damascene method of making a nonvolatile memory device
#94 | 2012-01-05Ultrahigh density vertical NAND memory device and method of making thereof
#95 | 2011-12-22Composition of memory cell with resistance-switching layers
#96 | 2011-12-22Memory cell with resistance-switching layers
#97 | 2011-12-22Method of fabricating non-volatile memory with flat cell structures and air gap isolation
#98 | 2011-08-04NON-VOLATILE MEMORY CELL CONTAINING NANODOTS AND METHOD OF MAKING THEREOF
#99 | 2011-07-28Damascene method of making a nonvolatile memory device
#100 | 2010-09-23Spacer patterns using assist layer for high density semiconductor devices
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