Christopher J. Petti

ADDRESS PATH ROUTING REDUCTION STRATEGY FOR NONVOLATILE MEMORY DECODERS

APPARATUS AND METHODS FOR REDUCING NEAR-NEAR - FAR-FAR MEMORY CELL RESISTANCE DIFFERENCES IN MEMORY ARRAYS

APPARATUS AND METHODS FOR REFERENCE READ TECHNIQUES FOR THRESHOLD SELECTOR DEVICE MEMORY

SELECTOR ONLY MEMORY WRITE OPERATION

CIRCUIT SNAPBACK AND CHARGE DIVERSION FOR CROSS-POINT ARRAYS

BIPOLAR DECODERS FOR NONVOLATILE MEMORY

APPARATUS AND METHODS FOR DECODER MODULE ARCHITECTURES FOR NON-VOLATILE MEMORY

DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY

THREE-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS

MEMORY STRUCTURE OF THREE-DIMENSIONAL NOR MEMORY STRINGS OF CHANNEL-ALL-AROUND FERROELECTRIC MEMORY TRANSISTORS AND METHOD OF FABRICATION

CURRENT SOURCE FOR READ OF PROGRAMMABLE RESISTANCE MEMORY CELLS

DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAFER BONDING

Three-dimensional memory string array of thin-film ferroelectric transistors

Device with embedded high-bandwidth, high-capacity memory using wafer bonding

THREE-DIMENSIONAL MEMORY STRING ARRAY OF THIN-FILM FERROELECTRIC TRANSISTORS FORMED WITH AN OXIDE SEMICONDUCTOR CHANNEL IN A CHANNEL LAST PROCESS

THREE-DIMENSIONAL NOR MEMORY STRING ARRAYS OF THIN-FILM FERROELECTRIC TRANSISTORS

3-dimensional memory string array of thin-film ferroelectric transistors

Semiconductor memory device with write disturb reduction

Quasi-volatile memory with reference bit line structure

Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensional NOR memory string array

Memory device including modular memory units and modular circuit units for concurrent memory operations

Overwrite read methods for resistance switching memory devices

OVERWRITE READ METHODS FOR MEMORY DEVICES

ONE SELECTOR ONE RESISTOR MRAM CROSSPOINT MEMORY ARRAY FABRICATION METHODS

Methods of forming a phase change memory with vertical cross-point structure

Magnetic random-access memory with selector voltage compensation

Three terminal isolation elements and methods

Device with embedded high-bandwidth, high-capacity memory using wafer bonding

Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same

Three terminal isolation elements and methods

Three dimensional ferroelectric memory

Content addressable memory using threshold-adjustable vertical transistors and methods of forming the same

Content addressable memory using threshold-adjustable vertical transistors and methods of forming the same

Electrostatic discharge protection devices including a field-induced switching element

Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same

Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same

VERTICAL 1T FERROELECTRIC MEMORY CELLS, MEMORY ARRAYS AND METHODS OF FORMING THE SAME

Methods of forming a phase change memory with vertical cross-point structure

Multi-state phase change memory device with vertical cross-point structure

Multi-state and confined phase change memory with vertical cross-point structure

Apparatus and method for identifying memory cells for data refresh based on monitor cell in a resistive memory device

Non-volatile memory system with serially connected non-volatile reversible resistance-switching memory cells

Process for fabricating three dimensional non-volatile memory system

Memory cell for non-volatile memory system

Methods and apparatus for three-dimensional nonvolatile memory

Three-level ferroelectric memory cell using band alignment engineering

Device with sub-minimum pitch and method of making

Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof

Three-dimensional memory device with vertical semiconductor bit lines located in recesses and method of making thereof

Vacancy-modulated conductive oxide resistive RAM device including an interfacial oxygen source layer

Memory cells including vertically oriented adjustable resistance structures

Memory cells including vertically oriented adjustable resistance structures

Content addressable memory cells and memory arrays

Silicided bit line for reversible-resistivity memory

Content addressable memory cells, memory arrays and methods of forming the same

Interleaved grouped word lines for three dimensional non-volatile storage

Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same

Vertical 1T-1R memory cells, memory arrays and methods of forming the same

Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning

DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME

NONVOLATILE MEMORY CELL COMPRISING A DIODE AND A RESISTANCE-SWITCHING MATERIAL

Mobile electronic device comprising an ultrathin sapphire cover plate

EPITAXIAL GROWTH ON THIN LAMINA

Silicon carbide lamina

Method for reducing dielectric overetch when making contact to conductive features

Method for fabricating backside-illuminated sensors

MULTI-LAYER METAL SUPPORT

Asymmetric surface texturing for use in a photovoltaic cell and method of making

Nonvolatile memory cell comprising a diode and a resistance-switching material

Photovoltaic Cell Comprising A Thin Lamina Having A Rear Junction And Method Of Making

Dense arrays and charge storage devices

Method to form a device by constructing a support element on a thin semiconductor lamina

Intermetal stack for use in a photovoltaic cell

Back-contact photovoltaic cell comprising a thin lamina having a superstrate receiver element

Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars

Zener diode within a diode structure providing shunt protection

Method to form a device by constructing a support element on a thin semiconductor lamina

Method to form a device including an annealed lamina and having amorphous silicon on opposing faces

METHOD FOR REDUCING DIELECTRIC OVERETCH USING A DIELECTRIC ETCH STOP AT A PLANAR SURFACE

Method for reducing dielectric overetch when making contact to conductive features

Asymmetric surface texturing for use in a photovoltaic cell and method of making

DENSE ARRAYS AND CHARGE STORAGE DEVICES

Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning

Methods of forming pillars for memory cells using sequential sidewall patterning

PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA HAVING EMITTER FORMED AT LIGHT-FACING AND BACK SURFACES

Nonvolatile memory cell comprising a diode and a resistance-switching material

Method for reducing dielectric overetch using a dielectric etch stop at a planar surface

Three dimensional hexagonal matrix memory array

Method to make electrical contact to a bonded face of a photovoltaic cell

BACK-CONTACT PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA HAVING A SUPERSTRATE RECEIVER ELEMENT

PHOTOVOLTAIC CELL COMPRISING AN MIS-TYPE TUNNEL DIODE

Method for making a photovoltaic cell comprising contact regions doped through a lamina

Photovoltaic cell comprising contact regions doped through a lamina

FRONT CONNECTED PHOTOVOLTAIC ASSEMBLY AND ASSOCIATED METHODS

METHOD TO MITIGATE SHUNT FORMATION IN A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA

Photovoltaic cell comprising a thin lamina having a rear junction and method of making

PHOTOVOLTAIC MODULE COMPRISING THIN LAMINAE CONFIGURED TO MITIGATE EFFICIENCY LOSS DUE TO SHUNT FORMATION

Method to form a photovoltaic cell comprising a thin lamina

Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars

Asymmetric surface texturing for use in a photovoltaic cell and method of making