Santa Clara, California
United States
25
2026-04-02
The entities that hold a legal rights for patent applications filed by inventor Wang Wei:
Wei Wang from Santa Clara, US has applied for patents for these inventions. The list has both pending applications and granted patents:
SYSTEMS AND METHODS FOR PRESENTING A VIRTUAL REPRESENTATION IN A THREE-DIMENSIONAL ENVIRONMENT
#2 | 2025-02-27METHODS FOR MANAGING SPATIALLY CONFLICTING VIRTUAL OBJECTS AND APPLYING VISUAL EFFECTS
#3 | 2025-01-02SYSTEMS AND METHODS FOR MANAGING DISPLAY OF PARTICIPANTS IN REAL-TIME COMMUNICATION SESSIONS
#4 | 2024-12-05PORTAL CONTENT FOR COMMUNICATION SESSIONS
#5 | 2023-07-20METHODS AND SYSTEMS FOR TRAINING AND USING PREDICTIVE RISK MODELS IN SOFTWARE APPLICATIONS
#6 | 2023-07-20EFFICIENT USE OF COMPUTING RESOURCES FOR OPTIMIZATION OF NON-CONVEX FUNCTIONS
#7 | 2023-02-16Machine learning accelerator mechanism
#8 | 2022-02-10MACHINE LEARNING PLATFORM FOR GENERATING RISK MODELS
#9 | 2021-11-04Machine learning network model compression
#10 | 2021-04-29GENERATING A COMPRESSED REPRESENTATION OF A NEURAL NETWORK WITH PROFICIENT INFERENCE SPEED AND POWER CONSUMPTION
#11 | 2021-04-08Three-dimension (3D) assisted personalized home object detection
#12 | 2020-04-16Multi-stage image recognition for a non-ideal environment
#13 | 2019-12-12METHODS AND APPARATUS FOR MAGNETRON ASSEMBLIES IN SEMICONDUCTOR PROCESS CHAMBERS
#14 | 2019-07-18Robot navigation and object tracking
#15 | 2019-07-04Machine learning accelerator mechanism
#16 | 2019-05-23Three-dimensional (3D) reconstructions of dynamic scenes using a reconfigurable hybrid imaging system
#17 | 2018-09-06Fine-grained object recognition in robotic systems
#18 | 2018-06-21Simultaneous localization and mapping with reinforcement learning
#19 | 2015-06-11Battery charging circuit with serial connection of MOSFET and an enhancement mode JFET configured as reverse blocking diode with low forward voltage drop
#20 | 2012-03-29Semiconductor device die with integrated MOSFET and low forward voltage diode-connected enhancement mode JFET and method
#21 | 2011-03-31Reduced mask configuration for power mosfets with electrostatic discharge (ESD) circuit protection
#22 | 2009-07-02Reduced mask configuration for power MOSFETs with electrostatic discharge (ESD) circuit protection
#23 | 2008-11-27Layouts for multiple-stage ESD protection circuits for integrating with semiconductor power device
#24 | 2005-11-17Controlled multi-step magnetron sputtering process
#25 | 2005-03-17Multi-step magnetron sputtering process
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