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Patent application title:

INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME

Publication number:

US20100187651A1

Publication date:
Application number:

12/578,382

Filed date:

2009-10-13

Abstract:

Aspects of the invention are directed towards an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.

Inventors:

Assignee:

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Classification:

  1. Electricity
  2. Basic electric elements

H01L24/83 »  CPC main

Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

H01L21/4821 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups -; Conductive parts Flat leads, e.g. lead frames with or without insulating supports

H01L21/486 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups -; Conductive parts; Leads on or in insulating or insulated substrates, e.g. metallisation Via connections through the substrate with or without pins

H01L21/56 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups  - , e.g. sealing of a cap to a base of a container Encapsulations, e.g. encapsulation layers, coatings

H01L21/6835 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support

H01L21/768 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof; Manufacture of specific parts of devices defined in group Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

H01L23/49816 »  CPC further

Details of semiconductor or other solid state devices; Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered constructions; Leads, on insulating substrates,; Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]

H01L23/49827 »  CPC further

Details of semiconductor or other solid state devices; Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered constructions; Leads, on insulating substrates, Via connections through the substrates, e.g. pins going through the substrate, coaxial cables

H01L23/49894 »  CPC further

Details of semiconductor or other solid state devices; Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered constructions; Leads, on insulating substrates, characterised by the materials Materials of the insulating layers or coatings

H01L23/5389 »  CPC further

Details of semiconductor or other solid state devices; Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures

H01L24/11 »  CPC further

Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bump connectors ; Manufacturing methods related thereto Manufacturing methods

H01L24/18 »  CPC further

Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto High density interconnect [HDI] connectors; Manufacturing methods related thereto

H01L24/19 »  CPC further

Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; High density interconnect [HDI] connectors; Manufacturing methods related thereto Manufacturing methods of high density interconnect preforms

H01L24/24 »  CPC further

Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; High density interconnect [HDI] connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector

H01L24/82 »  CPC further

Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]

H01L24/96 »  CPC further

Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

H01L21/568 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups  - , e.g. sealing of a cap to a base of a container; Encapsulations, e.g. encapsulation layers, coatings Temporary substrate used as encapsulation process aid

H01L2221/68345 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by; Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates

H01L2221/68359 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by; Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers

H01L2221/68372 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by; Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto

H01L2221/68377 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by; Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device

H01L2221/68381 »  CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by; Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support Details of chemical or physical process used for separating the auxiliary support from a device or wafer

H01L2224/04105 »  CPC further

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Structure, shape, material or disposition of the bonding areas prior to the connecting process Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages

H01L2224/12105 »  CPC further

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bump connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the bump connectors prior to the connecting process Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages

H01L2224/18 »  CPC further

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto High density interconnect [HDI] connectors; Manufacturing methods related thereto

H01L2224/2518 »  CPC further

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; High density interconnect [HDI] connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors; Disposition being disposed on at least two different sides of the body, e.g. dual array

H01L2224/8385 »  CPC further

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector; Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester

H01L2924/01006 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Carbon [C]

H01L2924/01013 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Aluminum [Al]

H01L2924/01029 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Copper [Cu]

H01L2924/01033 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Arsenic [As]

H01L2924/01047 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Silver [Ag]

H01L2924/01078 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Platinum [Pt]

H01L2924/01079 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Gold [Au]

H01L2924/01082 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Lead [Pb]

H01L2924/09701 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by with a principal constituent of the material being a combination of two or more materials provided in the groups  - ; Glass-ceramics, e.g. devitrified glass Low temperature co-fired ceramic [LTCC]

H01L2924/14 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of semiconductor or other solid state devices to be connected; Device type Integrated circuits

H01L2924/15311 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of package parts other than the semiconductor or other solid state devices to be connected; Die mounting substrate; Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

H01L2924/19041 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected; Structure; Component type being a capacitor

H01L2924/19042 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected; Structure; Component type being an inductor

H01L2924/19043 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected; Structure; Component type being a resistor

H01L2924/181 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of package parts other than the semiconductor or other solid state devices to be connected Encapsulation

H01L2924/00 »  CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by

H01L23/495 IPC

Details of semiconductor or other solid state devices; Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered constructions Lead-frames or other flat leads

H01L27/06 IPC

Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration

H01L21/50 IPC

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups  - , e.g. sealing of a cap to a base of a container

Description

This application claims the benefit of U.S. Provisional Patent Application No. 61/147,430, filed on Jan. 26, 2009, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to an integrated circuit package and method of forming the same, and more particularly to a redistributed chip packaging for an integrated circuit.

2. Discussion of the Related Art

With continuously decreasing semiconductor device dimensions and increasing device packaging densities, the packaging of semiconductor devices has continued to gain in importance. In the electronics industry, the continuing goal has been to reduce the size of electronic devices such as in digital cameras and camcorders. Metal interconnects, thereby including points of metal contact solder bumps that connect a semiconductor to surrounding circuits, increasingly become important.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an integrated circuit package and method of forming the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.

An advantage of an embodiment of the invention is to provide reduced processing steps for foaming a chip packing.

Another advantage of an embodiment of the invention is to provide a reduced cost of forming a chip packing.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages and in accordance with the purpose of the invention, an embodiment of the invention is directed towards an integrated circuit package. The integrated circuit package includes an integrated circuit having a protective material on at least a portion of the integrated circuit. A lead frame is coupled to the integrated circuit and a conductive layer is also coupled to the interconnect. A solder ball is coupled to the conductive layer and a passivation layer is on the conductive layer. Active and passive components are electrically coupled to the integrated circuit.

In another aspect, an embodiment of the invention is directed towards a method of forming an integrated circuit package. The method includes forming a lead frame including a first portion and a second portion. The first portion and the second portion of the lead frame intersect at an angle ranging from about 45 degrees to about 135 degrees. An adhesive material is formed on the first portion of the lead frame and a carrier is attached to the lead frame with the adhesive material. An integrated circuit is also attached to the adhesive material. Interconnects are formed on the integrated circuit and protective material is formed on the integrated circuit.

In another aspect, an embodiment of the invention is directed towards a method of making an integrated circuit package. The method includes forming a lead frame including a first portion and a second portion. The first portion and the second portion of the lead frame intersect at an angle ranging from about 45 degrees to about 135 degrees. A double sided thermal tape is adhered to a bottom surface of the first portion of the lead frame; attaching a carrier to the lead frame with the thermal double-sided thermal tape is also part of the method. The method further includes attaching an integrated circuit to the thermal double-sided adhesive tape adjacent to the first portion of the lead frame and forming at least one pillar interconnect on the integrated circuit. A compressive compound is formed over the integrated circuit as well as over the first and second portions of the lead frame. The compressive compound is hardened by heating the compressive compound to a temperature in the range of about 120° C. to about 150° C.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

In the drawings:

FIG. 1A illustrates a cross-sectional view of manufacturing a lead frame of the integrated circuit package of FIG. 1 according to an embodiment of the invention;

FIG. 1B illustrates a top-down view of the lead frame in FIG. 1A;

FIG. 2 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package of FIG. 1;

FIG. 3 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package of FIG. 1;

FIG. 4 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package of FIG. 1;

FIG. 5 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package of FIG. 1; and

FIG. 6 illustrates a completed integrated circuit package.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Reference will now be made in detail to an embodiment of the present invention, an example of which is illustrated in the accompanying drawings.

FIG. 1A illustrates a cross-sectional view of manufacturing an integrated circuit package according to an embodiment of the invention.

FIG. 1A illustrates forming a lead frame 100 having a first portion 102 and a second portion 104. The first portion 102 and the second portion 104 intersect forming an angle 106 ranging from about 45 degrees to about 135 degrees. In a preferred embodiment, the angle ranges from about 85 degrees to about 95 degrees. In a more preferred embodiment, the angle is about 90 degrees. The lead frame 100 comprises a conductive material. The conductive material may be a single material or an alloy material such as aluminum, gold, copper, combinations thereof, and the like. Now referring to FIG. 1B, it shows a top-down view of the lead frame 100. The lead frame is manufactured by forming the conductive material via stamping or etching as known in the art. In a preferred embodiment, the conductive material is stamped to form a plurality of open spaces 108 and bent into the desired angle 106 as shown in FIG. 1A.

FIG. 2 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package after forming the lead frame.

Referring to FIG. 2, an adhesive material 202 is formed on the bottom portion of the lead frame 100. In a preferred embodiment, the adhesive material 202 is double-sided thermal release tape such as 3195V by Nitto Denko, Japan. The double-sided thermal release tape is capable of being removed after thermo process at a high temperature ranging from about 175° C. to about 260° C. The adhesive material 202 is attached to a bottom surface of the lead frame and/or a carrier 204; next the carrier 204 is attached to an opposite surface of the adhesive material 202. The carrier 204 is for transportation of the apparatus and may include materials such as plastics, glass (e.g., low temperature CT glass), ceramics, steel, combinations thereof, and the like.

An integrated circuit chip 206 is attached to the adhesive material 202. The integrated circuit chip 206 is arranged between second portions 104 of the lead frame 100. At least one interconnect 208 is formed on the integrated circuit chip 206. In a preferred embodiment, the interconnect 208 includes a conductive material, e.g., copper, gold, pewter, combinations thereof, and the like, formed by plating as known in the art. In a preferred embodiment, the interconnect is a copper pillar bump. Of course, other conductive materials may also be used, such as alloys and the like.

FIG. 3 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package after attaching a carrier.

Referring to FIG. 3, a protective material 302 is formed over the structure in FIG. 2. The protective material is an encapsulant of material such as epoxy, plastic, polymers, combinations thereof, and the like. In a preferred embodiment, the protective material is an epoxy compressive molding compound. The protective material may either come in powder or liquid form. If in powder form, the powder needs to be processed before applying. The compressive molding compound is capable of being hardened during a molding process. In this embodiment, a mold (not shown) is affixed from the top and bottom and heated for the desired time and to the desired temperature to harden the protective material. After which, the mold is released, thereby forming a hardened protective material 302.

In a preferred embodiment, the hardening process includes heating the compound to a temperature ranging from about 120° C. to about 150° C. for a time ranging from about 2 to about 10 minutes. Also, in the preferred embodiment, the epoxy part is R4212 epoxy molding compound from Nagase Corp. of Japan.

FIG. 4 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package after forming the compressive molding compound.

Referring to FIG. 4, the adhesive material 202 and carrier 204 are removed by heating the apparatus to a thermal release temperature, e.g., a temperature ranging from about 175° C. to about 260° C. In a preferred embodiment, the apparatus is heated to a temperature of about 260° C.

FIG. 5 illustrates a cross-sectional view of an intermediate stage of manufacturing the integrated circuit package after forming the compressive molding compound.

Referring to FIG. 5, an upper and lower portion of the compressive molding compound 302 is removed. Removing these portions may be accomplished with grinding and/or polishing procedures as known in the art such as wheel silicon grinding. In a preferred embodiment, the compressive molding on the lower surface is grinded to remove the second portion 104 of the lead frame 100, e.g., about 115 μm of the second portion 104. The upper surface of the compressive molding compound 302 is removed to expose a surface of the interconnect 208 and the first portion 102 of the lead frame 100.

FIG. 6 illustrates a completed integrated circuit package.

Referring to FIG. 6, a first metallization layer is formed on a first surface of the compressive molding 302. A second metallization layer is formed on a second surface of the compressive molding 302. The first and second metallization layers are formed of conductive material to a thickness ranging from about 3 μm to about 10 μM via chemical vapor deposition, physical vapor deposition, and the like. The first metallization layer is etched to form interconnect traces 602. The second metallization layer is etched to form interconnect traces 604. The first and second metallization layers may be faulted of different materials. In a preferred embodiment, the first and second metallization layers consist of copper, aluminum, gold, or alloys thereof.

A first passivation layer 606 is formed on the interconnect traces 602 and a second passivation layer 608 is formed on the interconnect traces 604. The first passivation layer 606 is etched to form a contact hole 610. The first and second passivation layers are formed of insulative material via polymers, e.g., photosensitive liquid polymers. The insulating materials may include parylene, polyimide, benzocyclobutene (BCB), polybenzoxazole. (PBO), combinations thereof, and the like. The first and second passivation layers may be formed of different materials. A solder ball 612 is formed in the contact hole 610. The solder ball 612 is formed from conventional processes and may include a conductive material, such as silver, copper, tin, combinations thereof, and the like. Components 614, such as passive or active components including, for example, capacitors, resistors, transistors, inductors, combinations thereof, and the like, are attached to the interconnect traces 604.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

What is claimed is:

1. An integrated circuit package, comprising:

an integrated circuit;

a protective material on at least a portion of the integrated circuit;

a lead frame coupled to the integrated circuit;

a conductive layer coupled to the interconnect;

a solder ball coupled the conductive layer; and

a passivation layer on the conductive layer.

2. The integrated circuit package of claim 1, wherein the protective material comprises a compressive molding compound.

3. The integrated circuit package of claim 2, wherein the compressive molding compound comprises epoxy.

4. The integrated circuit package of claim 1, wherein the lead frame comprises a material selected from the group consisting of Al, Au, Cu, and combinations thereof.

5. The integrated circuit package of claim 1, wherein the passivation layer comprises an insulating polymer selected from the group consisting of parylene, polyimide, benzocyclobutene (BCB), and polybenzoxazole (PBO).

6. The integrated circuit package of claim 1, wherein the lead frame comprises a conductive material selected from the group consisting of Au, Al, Cu, Ti, and alloys of the same.

7. The integrated circuit package of claim 1, further comprising at least one of active and passive components electrically coupled to the integrated circuit.

8. A method of forming an integrated circuit package, comprising the steps of:

forming a lead frame comprising a first portion and a second portion, wherein the first portion and the second portion intersect at an angle ranging from about 45 degrees to about 135 degrees;

forming an adhesive material on the first portion of the lead frame;

attaching a carrier to the lead frame with the adhesive material;

attaching an integrated circuit to the adhesive material;

forming an interconnect on the integrated circuit; and

forming a protective material on the integrated circuit.

9. The method of claim 8, wherein the angle is in the range from about 85 degrees to about 95 degrees.

10. The method of claim 8, wherein forming the protective layer comprises the step of:

heating an epoxy material to a temperature in the range from about 120° C. to about 150° C. to harden the epoxy material.

11. The method of claim 8, further comprising removing the carrier and the adhesive material by heating an epoxy material to a temperature from about 175° C. to about 260° C. to thermally release the adhesive material and carrier.

12. The method of claim 11, further comprising the steps:

removing a portion of the hardened epoxy material to expose the interconnect and the first portion of the lead frame; and

removing the second portion of the lead frame.

13. The method of claim 12, wherein removing the portion of hardened epoxy material comprises grinding an upper surface of the hardened compound.

14. The method of claim 12, further comprising the steps of:

forming a conductive material on the hardened compound;

forming a passivation layer on the conductive material; and

faulting a solder ball on the passivation layer, wherein the solder ball is electrically coupled to the conductive material.

15. A method of making an integrated circuit package, comprising the steps of:

forming a lead frame comprising a first portion and a second portion, wherein the first portion and the second portion intersect at an angle ranging from about 45 degrees to about 135 degrees;

adhering a double-sided thermal tape to a bottom surface of the first portion of the lead frame;

attaching a carrier to the lead frame with the double-sided thermal tape;

attaching an integrated circuit to the double-sided thermal adhesive tape adjacent to the first portion of the lead frame;

forming at least one pillar interconnect on the integrated circuit;

forming a compressive compound over the integrated circuit and the first and second portions of the lead frame; and

hardening the compressive compound by heating the compressive compound to a temperature in the range from about 120° C. to about 150° C.

16. The method of claim 15, further comprising the steps:

removing a portion of the hardened molding to expose the pillar interconnect and the second portion of the lead frame; and

removing the first portion of the lead frame.

17. The method of claim 16, wherein the removing the portion of compressive molding step comprises grinding an upper surface of the compressive molding.

18. The method of claim 17, further comprising the steps of:

forming a conductive material on the hardened molding;

forming a first passivation layer on an upper surface of the conductive material;

forming a second passivation layer on a lower surface of the compressive molding material; and

forming a solder ball on the first passivation layer, wherein the solder ball is electrically coupled to the conductive material.

19. The method of claim 15, wherein the compressive molding material comprises an epoxy material.

20. The method of claim 18, further comprising the steps of attaching a component to the lower surface of the compressive molding.

Resources

Images & Drawings included:

Fig. 01 - INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME
Fig. 01
Fig. 02 - INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME
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Fig. 03 - INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME
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Fig. 04 - INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING THE SAME
Fig. 04

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