209729 ⎘
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bump connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector; Disposition the bump connector being at least partially embedded in the surface
PACKAGE COMPRISING A SUBSTRATE WITH VIA INTERCONNECT WITH VERTICAL WALLS
#2SEMICONDUCTOR PACKAGE
#3SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
#4SEMICONDUCTOR PACKAGE
#5MEMORY DEVICE AND METHOD OF ASSEMBLING SAME
#6Manufacturing method of semiconductor package
#7Semiconductor packaging substrate fine pitch metal bump and reinforcement structures
#8Semiconductor package and manufacturing method thereof
#9Semiconductor devices including through-silicon-vias and methods of manufacturing the same and semiconductor packages including the semiconductor devices
#10SEMICONDUCTOR PACKAGE
#11Semiconductor device package and method of manufacturing the same
#12Semiconductor die singulation and structures formed thereby
#13Forming bonding structures by using template layer as templates
#14Semiconductor memory device and method of manufacturing the same
#15Semiconductor package and method of manufacturing the same
#16Stacked semiconductor packages
#17Semiconductor device
#18Nanoscale interconnect array for stacked dies
#19Bonding interposer and integrated circuit chip, and ultrasound probe using the same
#20Semiconductor package and method of manufacturing the same
#21Process for manufacturing a flip chip semiconductor package and a corresponding flip chip package
#22Method of fabricating a semiconductor package
#23Semiconductor die singulation and structures formed thereby
#24Semiconductor device
#25Lateral vias for connections to buried microconductors and methods thereof
#26Forming bonding structures by using template layer as templates
#27Semiconductor devices including through-silicon-vias and methods of manufacturing the same and semiconductor packages including the semiconductor devices
#28Semiconductor die singulation and structures formed thereby
#29Semiconductor device including conductive layer and conductive pillar disposed on conductive layer and method of manufacturing the same
#30Nanoscale interconnect array for stacked dies
#31Method and apparatus for connecting packages onto printed circuit boards
#32Method for producing a chip assemblage
#33ELECTRONIC PART, ELECTRONIC DEVICE, AND ELECTRONIC APPARATUS
#34Semiconductor device and method of manufacturing the same
#35Semiconductor device and method for manufacturing the same
#36Apparatus for stacked semiconductor packages and methods of fabricating the same
#37Semiconductor device and method for producing semiconductor device
#38Chip package and manufacturing method thereof
#39Semiconductor device and method of manufacturing same
#40System and method for an improved fine pitch joint
#41Redistribution film for IC package
#42Method and apparatus for connecting packages onto printed circuit boards
#43STACKED SEMICONDUCTOR PACKAGES, METHODS FOR FABRICATING THE SAME, AND /OR SYSTEMS EMPLOYING THE SAME
#44PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME
#45Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects
#46Thin wafer handling and known good die test method
#47Semiconductor device and method of making bumpless flipchip interconnect structures
#48Electronic components assembly
#49Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
#50Semiconductor device and method of forming compliant conductive interconnect structure in flipchip package
#51DEVICE SUBSTRATE AND METHOD FOR MANUFACTURING SAME
#52Semiconductor device and method of manufacturing the same
#53Controlling Solder Bump Profiles by Increasing Heights of Solder Resists
#54Scalable transfer-join bonding lock-and-key structures
#55Systems employing a stacked semiconductor package
#56Electrical assembly
#57Solder limiting layer for integrated circuit die copper bumps
#58Semiconductor device and method of manufacturing the same
#59METHOD OF INTERCONNECTING CHIPS USING CAPILLARY MOTION
#60Lock and key through-via method for wafer level 3 D integration and structures produced
#61Method of manufacturing chip-on-chip semiconductor device
#62Apparatus and methods of testing and assembling bumped devices using an anisotropically conductive layer
#63Process to allow electrical and mechanical connection of an electrical device with a face equipped with contact pads
#64Lateral vias for connections to buried microconductors