Cupertino, California
United States
134
2024-06-20
The entities that hold a legal rights for patent applications filed by inventor Rabkin Peter:
Peter Rabkin from Cupertino, US has applied for patents for these inventions. The list has both pending applications and granted patents:
THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAME
#2 | 2024-06-20THREE-DIMENSIONAL NOR ARRAY AND METHOD OF MAKING THE SAME
#3 | 2023-11-09MEMORY DEVICE INCLUDING COMPOSITE METAL OXIDE SEMICONDUCTOR CHANNELS AND METHODS FOR FORMING THE SAME
#4 | 2023-11-09MEMORY DEVICE INCLUDING COMPOSITE METAL OXIDE SEMICONDUCTOR CHANNELS AND METHODS FOR FORMING THE SAME
#5 | 2023-11-09MEMORY DEVICE INCLUDING COMPOSITE METAL OXIDE SEMICONDUCTOR CHANNELS AND METHODS FOR FORMING THE SAME
#6 | 2023-08-10Bonded assembly containing different size opposing bonding pads and methods of forming the same
#7 | 2023-05-25Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making the same
#8 | 2023-05-25Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof
#9 | 2023-05-25Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof
#10 | 2023-05-25Three dimensional memory device containing resonant tunneling barrier and high mobility channel and method of making thereof
#11 | 2023-02-09Bonded assembly including inter-die via structures and methods for making the same
#12 | 2023-02-09Reliability compensation for uneven NAND block degradation
#13 | 2023-01-12Bonded assembly including an airgap containing bonding-level dielectric layer and methods of forming the same
#14 | 2022-11-17Capacitor structure including bonding pads as electrodes and methods of forming the same
#15 | 2022-11-03Bonded assembly employing metal-semiconductor bonding and metal-metal bonding and methods of forming the same
#16 | 2022-09-29Memory device including a ferroelectric semiconductor channel and methods of forming the same
#17 | 2022-09-29MEMORY DEVICE INCLUDING A FERROELECTRIC SEMICONDUCTOR CHANNEL AND METHODS OF FORMING THE SAME
#18 | 2022-08-04Bonded semiconductor die assembly with metal alloy bonding pads and methods of forming the same
#19 | 2022-06-30Bonded three-dimensional memory devices with backside source power supply mesh and methods of making the same
#20 | 2022-06-02Interfacial tilt-resistant bonded assembly and methods for forming the same
#21 | 2022-05-12Bonded assembly formed by hybrid wafer bonding using selectively deposited metal liners
#22 | 2022-03-24BONDED ASSEMBLY INCLUDING INTERCONNECT-LEVEL BONDING PADS AND METHODS OF FORMING THE SAME
#23 | 2022-03-03Three-dimensional memory device with vertical field effect transistors and method of making thereof
#24 | 2022-03-03Three-dimensional memory device with vertical field effect transistors and method of making thereof
#25 | 2022-03-03Three-dimensional memory device with vertical field effect transistors and method of making thereof
#26 | 2022-02-10Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same
#27 | 2022-02-10Three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same
#28 | 2021-12-30Three-dimensional memory device including III-V compound semiconductor channel layer and method of making the same
#29 | 2021-12-30Three-dimensional memory device including III-V compound semiconductor channel layer and method of making the same
#30 | 2021-12-02Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
#31 | 2021-12-02Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
#32 | 2021-12-02Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
#33 | 2021-10-21Bonded assembly containing low dielectric constant bonding dielectric material
#34 | 2021-10-14BONDED ASSEMBLY CONTAINING BONDING PADS SPACED APART BY POLYMER MATERIAL, AND METHODS OF FORMING THE SAME
#35 | 2021-09-02Semiconductor die containing silicon nitride stress compensating regions and method for making the same
#36 | 2021-08-26Ferroelectric memory devices containing a two-dimensional charge carrier gas channel and methods of making the same
#37 | 2021-07-15Bonding pads including interfacial electromigration barrier layers and methods of making the same
#38 | 2021-05-27Bonded assembly containing horizontal and vertical bonding interfaces and methods of forming the same
#39 | 2021-05-27Bonded assembly containing laterally bonded bonding pads and methods of forming the same
#40 | 2021-05-13Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same
#41 | 2021-03-25Ferroelectric memory devices with dual dielectric confinement and methods of forming the same
#42 | 2021-03-18Methods for reusing substrates during manufacture of a bonded assembly including a logic die and a memory die
#43 | 2021-03-04Embedded bonded assembly and method for making the same
#44 | 2021-03-04Temperature dependent impedance mitigation in non-volatile memory
#45 | 2021-02-18Programming to minimize cross-temperature threshold voltage widening
#46 | 2021-01-28Bonded die assembly containing partially filled through-substrate via structures and methods for making the same
#47 | 2020-12-17Bonded die assembly containing a manganese-containing oxide bonding layer and methods for making the same
#48 | 2020-12-10Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same
#49 | 2020-12-10Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same
#50 | 2020-10-29Porous barrier layer for improving reliability of through-substrate via structures and methods of forming the same
#51 | 2020-10-08Hot-cold VTH mismatch using VREAD modulation
#52 | 2020-09-17Three-dimensional memory device including liner free molybdenum word lines and methods of making the same
#53 | 2020-09-17Non-volatile memory with capacitors using metal under signal line or above a device capacitor
#54 | 2020-09-17Non-volatile memory with capacitors using metal under signal line or above a device capacitor
#55 | 2020-06-25Ferroelectric memory devices containing a two-dimensional charge carrier gas channel and methods of making the same
#56 | 2020-06-25Three-dimensional memory device with a graphene channel and methods of making the same
#57 | 2020-05-07Location dependent impedance mitigation in non-volatile memory
#58 | 2020-05-07Impedance mismatch mitigation scheme that applies asymmetric voltage pulses to compensate for asymmetries from applying symmetric voltage pulses
#59 | 2020-05-07Erase operation in 3D NAND flash memory including pathway impedance compensation
#60 | 2020-04-02Hot-cold VTH mismatch using VREAD modulation
#61 | 2020-02-13Three-dimensional memory device including liner free molybdenum word lines and methods of making the same
#62 | 2020-01-09Non-volatile memory with capacitors using metal under signal line or above a device capacitor
#63 | 2020-01-09Non-volatile memory with capacitors using metal under pads
#64 | 2020-01-02Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same
#65 | 2020-01-02Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same
#66 | 2019-06-11Metal contact via structure surrounded by an air gap and method of making thereof
#67 | 2018-10-30Multiple liner interconnects for three dimensional memory devices and method of making thereof
#68 | 2018-01-30Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof
#69 | 2017-11-14Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof
#70 | 2017-10-05NAND structure with tier select gate transistors
#71 | 2017-08-01Three-dimensional memory device having a transition metal dichalcogenide channel
#72 | 2017-07-183D NAND with partial block erase
#73 | 2017-06-20Reversible resistivity memory with crystalline silicon bit line
#74 | 2017-04-20Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices
#75 | 2017-04-20Ultrathin semiconductor channel three-dimensional memory devices
#76 | 2017-03-02NAND boosting using dynamic ramping of word line voltages
#77 | 2016-12-27Three-dimensional memory device containing CMOS devices over memory stack structures
#78 | 2016-12-08Method of making a three-dimensional memory device having a heterostructure quantum well channel
#79 | 2016-10-25Three dimensional memory device containing aluminum source contact via structure and method of making thereof
#80 | 2016-09-29Method of forming 3D vertical NAND with III-V channel
#81 | 2016-09-293D vertical NAND with III-V channel
#82 | 2016-09-20Memory cell with high-k charge trapping layer
#83 | 2016-08-23Three-dimensional memory device having a heterostructure quantum well channel
#84 | 2016-06-23Fabricating 3D NAND memory having monolithic crystalline silicon vertical NAND channel
#85 | 2016-06-14Method of forming memory cell with high-k charge trapping layer
#86 | 2016-05-263D NAND with oxide semiconductor channel
#87 | 2016-05-26NAND boosting using dynamic ramping of word line voltages
#88 | 2016-05-05Band gap tailoring for a tunneling dielectric for a three-dimensional memory structure
#89 | 2016-04-28Three dimensional NAND device containing fluorine doped layer and method of making thereof
#90 | 2016-04-21Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device
#91 | 2016-04-07Three dimensional NAND device with silicon germanium heterostructure channel
#92 | 2016-03-31Vertical memory device with bit line air gap
#93 | 2016-03-153D memory having crystalline silicon NAND string channel
#94 | 2016-01-05Vertical TFT with tunnel barrier
#95 | 2015-11-05Thin film transistor
#96 | 2015-11-03Three dimensional NAND devices with air gap or low-k core
#97 | 2015-10-29Vertical bit line wide band gap TFT decoder
#98 | 2015-03-193D non-volatile storage with transistor decoding structure
#99 | 2015-03-19Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device
#100 | 2015-03-123D non-volatile storage with wide band gap transistor decoder
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