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Patent application title:

METHOD OF MANUFACTURING A COMBINED MULTILAYER CIRCUIT BOARD HAVING EMBEDDED CHIPS

Publication number:

US20090056118A1

Publication date:

2009-03-05

Application number:

12/262,261

Filed date:

2008-10-31

Abstract:

A method has acts of providing at least two multilayer circuit boards, combining the at least two multilayer circuit boards to form a combined multilayer circuit board, forming multiple outer conductive vias, circuits and contacts on the combined multilayer circuit board. Each multilayer circuit board is fabricated by steps of preparing a single-layer printed circuit board having multiple chip sections, attaching at least one chip to the corresponding chip section, attaching a frame having multiple enclosures to the single-layer printed circuit board, attaching a semi-fluid glue sheet to the frame, vacuum pressing a conductive layer on the semi-fluid glue sheet and forming multiple conductive inner vias through the multilayer circuit board. The at least two multilayer circuit boards are combined by steps of reversing one of the multilayer circuit boards and vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board.

Inventors:

Roger CHANG 6 🇹🇼 Taoyuan Hsien, Taiwan

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Classification:

H05K1/187 » CPC main

Printed circuits; Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]; Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier

H05K1/187 » CPC main

H01L21/4857 » CPC further

Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof; Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer; Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups -; Conductive parts; Leads on or in insulating or insulated substrates, e.g. metallisation Multilayer substrates

H01L21/486 » CPC further

H01L23/5389 » CPC further

Details of semiconductor or other solid state devices; Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures

H01L24/97 » CPC further

Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

H01L25/0652 » CPC further

Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups - , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group the devices being arranged next and on each other, i.e. mixed assemblies

H01L25/50 » CPC further

Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group or

H05K1/186 » CPC further

H01L24/48 » CPC further

Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Wire connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

H01L2924/01005 » CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Boron [B]

H01L2924/01006 » CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Carbon [C]

H01L2924/01029 » CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Chemical elements Copper [Cu]

H01L2924/15153 » CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of package parts other than the semiconductor or other solid state devices to be connected; Die mounting substrate; Shape the die mounting substrate comprising a recess for hosting the device

H01L2924/1517 » CPC further

H01L2924/16195 » CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of package parts other than the semiconductor or other solid state devices to be connected; Cap; Shape Flat cap [not enclosing an internal cavity]

H01L2924/1627 » CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of package parts other than the semiconductor or other solid state devices to be connected; Cap; Disposition stacked type assemblies, e.g. stacked multi-cavities

H01L2924/19041 » CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected; Structure; Component type being a capacitor

H01L2924/19043 » CPC further

H05K3/28 » CPC further

Apparatus or processes for manufacturing printed circuits; Secondary treatment of printed circuits Applying non-metallic protective coatings

H05K3/28 » CPC further

Apparatus or processes for manufacturing printed circuits; Secondary treatment of printed circuits Applying non-metallic protective coatings

H05K3/4623 » CPC further

Apparatus or processes for manufacturing printed circuits; Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards

H05K3/4623 » CPC further

H05K3/4652 » CPC further

Apparatus or processes for manufacturing printed circuits; Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

H05K3/4652 » CPC further

H05K2201/0358 » CPC further

Indexing scheme relating to printed circuits covered by; Conductive materials; Structure of the conductor; Layered conductors or foils Resin coated copper [RCC]

H05K2201/0358 » CPC further

Indexing scheme relating to printed circuits covered by; Conductive materials; Structure of the conductor; Layered conductors or foils Resin coated copper [RCC]

H05K2201/09536 » CPC further

Indexing scheme relating to printed circuits covered by; Shape and layout; Shape and layout details of conductors; Conductive through-holes or vias Buried plated through-holes, i.e. plated through-holes formed in a core before lamination

H05K2201/09536 » CPC further

H05K2201/10674 » CPC further

Indexing scheme relating to printed circuits covered by; Details of components or other objects attached to or integrated in a printed circuit board; Details of electrical connections of non-printed components, e.g. special leads; Components characterised by their electrical contacts Flip chip

H05K2201/10674 » CPC further

H05K2203/063 » CPC further

Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by; Lamination of preperforated insulating layer

H05K2203/063 » CPC further

Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by; Lamination of preperforated insulating layer

H05K2203/068 » CPC further

Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by; Lamination Features of the lamination press or of the lamination process, e.g. using special separator sheets

H05K2203/068 » CPC further

H05K2203/085 » CPC further

Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by; Treatments involving gases Using vacuum or low pressure

H05K2203/085 » CPC further

Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by; Treatments involving gases Using vacuum or low pressure

Y10T29/49126 » CPC further

Metal working; Method of mechanical manufacture; Electrical device making; Conductor or circuit manufacturing; On flat or curved insulated base, e.g., printed circuit, etc. Assembling bases

Y10T29/49128 » CPC further

Metal working; Method of mechanical manufacture; Electrical device making; Conductor or circuit manufacturing; On flat or curved insulated base, e.g., printed circuit, etc. Assembling formed circuit to base

Y10T29/4913 » CPC further

Y10T29/49146 » CPC further

Y10T29/49155 » CPC further

Y10T29/49165 » CPC further

H01L2224/85 » CPC further

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector

H01L2224/81 » CPC further

H01L2224/83 » CPC further

H01L2224/97 » CPC further

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

H01L2224/73265 » CPC further

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being of different types provided for in two or more of groups; Location after the connecting process on different surfaces Layer and wire connectors

H01L2224/45099 » CPC further

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Wire connectors; Manufacturing methods related thereto; Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector; Core members of the connector Material

H01L2924/00014 » CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

H01L2924/207 » CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Parameters Diameter ranges

H01L2924/00011 » CPC further

Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by; Technical content checked by a classifier Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group

H01L2224/0401 » CPC further

Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by; Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto; Bonding areas; Manufacturing methods related thereto; Structure, shape, material or disposition of the bonding areas prior to the connecting process Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]

H05K3/30 IPC

Apparatus or processes for manufacturing printed circuits Assembling printed circuits with electric components, e.g. with resistor

H05K3/30 IPC

Apparatus or processes for manufacturing printed circuits Assembling printed circuits with electric components, e.g. with resistor

Description

CROSS REFERENCE

This is a divisional application of an U.S. application Ser. No. 11/511,462, filed on Aug. 29, 2006, which is now pending.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method, and more particularly to a method of manufacturing a combined multilayer circuit board, wherein the combined multilayer circuit board has chips embedded therein.

2. Description of Related Art

Passive elements, such as resistors or capacitors, are mounted upon the conventional circuit boards, such as motherboards or printed circuit boards. However, the advancement of semiconductor technology has resulted in electronic products being smaller and more multi-function. More functions the circuit boards have, more passive elements are necessary. Smaller size and multi-function electronic produces are in opposite positions.

To overcome the shortcomings, the present invention provides a method of manufacturing a combined multilayer circuit board having embedded chips to mitigate or obviate the aforementioned problems.

SUMMARY OF THE INVENTION

The main objective of the invention is to provide a method of manufacturing a combined multilayer circuit board, wherein the multilayer circuit board has chips embedded therein.

A method in accordance with the present invention comprises acts of (a) providing at least two multilayer circuit boards, (b) combining the at least two multilayer circuit boards to form a combined multilayer circuit board (c) forming multiple outer conductive vias in the combined multilayer circuit board and (d) forming circuits and contacts on the combined multilayer circuit board. In the (a) act, each multilayer circuit board is fabricated by steps of (a1) preparing a single-layer printed circuit board having multiple chip sections, (a2) attaching at least one chip to the corresponding chip sections of the single-layer printed circuit board, (a3) attaching a frame having multiple enclosures to the single-layer printed circuit board, (a4) attaching a semi-fluid glue sheet to the frame, (a5) vacuum pressing a conductive layer on the semi-fluid glue sheet and (a6) forming multiple conductive inner vias through the multilayer circuit board. The (b) act comprises steps of (b1) reversing one of the multilayer circuit boards and (b2) vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board. The (c) act drills multiple through holes through the combined multilayer circuit board and then electroplating peripheries defining the through holes to form multiple outer conductive vias. The (d) act etches patterns on the conductive layers and coats an insulating lacquer layer on a portion of the patterned conductive layers.

Other objectives, advantages and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a fabricating flow of manufacturing a multilayer circuit board consisting of a single-layer FR4 printed circuit board by a first embodiment of a manufacturing method in accordance with the present invention;

FIG. 2 is a partial perspective top view of the single-layer FR4 printed circuit board as shown in FIG. 1;

FIG. 3 is a partial perspective top view of a chip section of the single-layer FR4 printed circuit board as shown in FIG. 2;

FIG. 4 is an exploded perspective view of the FR4 printed circuit board as shown in FIG. 2 with a frame;

FIG. 5 is a fabricating flow of manufacturing another multilayer circuit board consisting of a single-layer cooper plate printed circuit board by a first embodiment of a manufacturing method in accordance with the present invention;

FIG. 6 is a partial perspective top view of the single-layer cooper plate printed circuit board as shown in FIG. 5;

FIG. 7 is an exploded perspective view of the cooper plate printed circuit board as shown in FIG. 6 with a frame;

FIG. 8 is a side view in partial section of a first embodiment of a combined multilayer circuit board fabricated with the multilayer circuit boards as shown in FIGS. 1 and 5 by the first embodiment of the manufacturing method in accordance with the present invention;

FIG. 9 is a side view in partial section of the combined multilayer circuit board as shown in FIG. 8 with multiple outer conductive vias, patterned conductive layers and insulating lacquer layer;

FIG. 10 is a perspective view of the combined multilayer circuit board as shown in FIG. 9;

FIG. 11 is a reverse perspective view of the combined multilayer circuit board as shown in FIG. 10;

FIG. 12 is a side view in partial section of a second embodiment of a combined multilayer circuit board manufactured by a second embodiment of a manufacturing method in accordance with the present invention;

FIG. 13 is a side view in partial section of a third embodiment of a combined multilayer circuit board manufactured by a third embodiment of a manufacturing method in accordance with the present invention; and

FIG. 14 is a side view in partial section of a fourth embodiment of a combined multilayer circuit board manufactured by a fourth embodiment of a manufacturing method in accordance with the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

A first embodiment of a method for manufacturing a combined multilayer circuit board having embedded chips in accordance with the present invention comprises acts of (a) providing two multilayer circuit boards, (b) combining the two multilayer circuit boards to form a combined multilayer circuit board (c) forming multiple outer conductive vias in the combined multilayer circuit board and (d) forming circuits and contacts on the combined multilayer circuit board.

In the (a) act, the two multilayer circuit boards are different and respectively fabricated by two specific fabricating processes.

With reference to FIGS. 1-4, one specific fabricating process of one multilayer circuit board has steps of:

(a11) preparing a single-layer FR4 printed circuit board (10) having multiple chip sections (11) respectively having a FR4 substrate (12), multiple conducting wires (13), an insulating coating (14) and multiple contacts (111),

(a12) attaching at least one chip (31, 32) to the corresponding chip sections (11) of the single-layer FR4 printed circuit board (10),

(a13) attaching a frame (40) having multiple enclosures (41) to the single-layer FR4 printed circuit board (10),

(a14) attaching a semi-fluid glue sheet (50) to the frame (40),

(a15) vacuum pressing a conductive layer (60) on the semi-fluid glue sheet (50), and

(a16) forming multiple conductive inner vias (71) through the multilayer circuit board.

With reference to FIGS. 1-3, in the (a11) step, the multiple chip sections (11) are arranged in matrix on the single-layer FR4 printed circuit board (10). The multiple conducting wires (13) are formed on the FR4 substrate (12) of each chip section (11). Each insulating coating (14) is coated on a portion of the multiple conducting wires (13) on each chip section (11). The contacts (111) are defined as the exposed portion of the multiple conducting wires (13).

The (a12) step attaches one chip (31, 32) to the corresponding chip section (11) of the single-layer FR4 printed circuit board (10). Each chip (31, 32) is electronically connected to the contacts (111) by a wire bonding or a solder bump bonding and may be chip-size resistor or chip-size capacitor.

With reference to FIG. 4, the (a13) step attaches a frame (40) to the single-layer FR4 printed circuit board (10). The frame (40) has multiple enclosures (41), and each enclosure (41) corresponds to one chip section (11) on the single-layer FR4 printed circuit board (10) to enclose the corresponding chip section (11) and the corresponding chip (31, 32).

The (a14) step attaches a semi-fluid clue sheet (50) to the frame (40) to cover the frame (40).

The (a15) step vacuum presses a conductive layer (60) on the semi-fluid glue sheet (50) to fill inside of the enclosures (41) with glue of the semi-fluid glue sheets (50) to encapsulate the chips (31, 32). Furthermore, each conductive layer (60) can be used to form a circuitry or terminals later.

The (a16) step drills multiple holes through the FR4 substrate (12), the conducting wires (13), the insulating coating (14), the frame (40), the semi-fluid glue sheet (50) and the conductive layer (60) in the multilayer circuit board and then electroplates peripheries defining the holes to form multiple inner conductive vias (71). The inner conductive vias (71) electronically connect the conducting wires (13) to the conductive layer (60) in the multilayer circuit board.

With reference to FIGS. 5-7, the other specific fabricating process is used to fabricate the other multilayer circuit board in (a) act and has steps of:

(a21) preparing a single-layer cooper plate printed circuit board (20) having multiple chip sections (21) respectively having a cooper plate substrate (22), multiple conducting wires (23), an insulating coating (24) and multiple contacts (211),

(a22) attaching at least one chip (31, 32) to the corresponding chip section (21) of the single-layer cooper plate printed circuit board (20),

(a23) attaching a frame (40) having multiple enclosures (41) to the single-layer cooper plate printed circuit board (20),

(a24) attaching a semi-fluid glue sheet (50) to the frame (40),

(a25) vacuum pressing a conductive layer (60) on the semi-fluid glue sheet (50),

(a26) removing the cooper plate substrate, and

(a27) forming multiple conductive inner vias (71) through the multilayer circuit board.

With reference to FIGS. 5 and 6, in the (a21) step, the multiple chip sections (21) are arranged in matrix on the single-layer cooper plate printed circuit board (20). The multiple conducting wires (23) are formed on the cooper plate substrate (22) of each chip section (21). Each insulating coating (24) is coated on a portion of the multiple conducting wires (23) on each chip section (21). The contacts (211) are defined as the exposed portion of the multiple conducting wires (23).

The (a22) step attaches one chip (31, 32) to the corresponding chip section (21) of the single-layer cooper plate printed circuit board (20). Each chip (31, 32) is electronically connected to the contacts (211) by a wire bonding or a solder bump bonding.

With reference to FIG. 7, the (a23) step attaches a frame (40) to the single-layer cooper plate printed circuit board (20). The frame (40) has multiple enclosures (41), and each enclosure (41) corresponds to one chip section (21) on the single-layer cooper plate printed circuit board (20) to enclose the corresponding chip section (21) and the chip (31, 32).

The (a24) step attaches a semi-fluid clue sheet (50) to the frame (40) to cover the frame (40).

The (a25) step vacuum presses a conductive layer (60) on the semi-fluid glue sheet (50) to fill inside of the enclosures (41) with glue of the semi-fluid glue sheets (50) to encapsulate the chips (31, 32). Furthermore, each conductive layer (60) can be used to form a circuitry or terminals later.

The (a26) step removes the cooper plate substrate (22) of the single-layer copper plate printed circuit board (20) by an etching process.

The (a27) step drills multiple holes through the cooper plate substrate (22), the conducting wires (23), the insulating coating (24), the frame (40), the semi-fluid glue sheet (50) and the conductive layer (60) in the multilayer circuit board and then electroplates peripheries defining the holes to form multiple inner conductive vias (71). The inner conductive vias (71) electronically connect the conducting wires (23) to the conductive layer (60) in the multilayer circuit board.

With reference to FIG. 8, the (b) act comprises steps of (b1) reversing one of the multilayer circuit boards and (b2) vacuum pressing other multilayer circuit board on the reversed multilayer circuit board.

The (b1) step reverses the multilayer circuit board consisted of the single-layer cooper plate printed circuit board (20).

The (b2) step vacuum presses the un-reversed multilayer circuit board consisting of the single-layer FR4 printed circuit board (10) and the reversed multilayer circuit boards consisting of the single-layer cooper plate printed circuit board (20) together with a glue layer (80). The glue layer (80) is sandwiched between the two multilayer circuit boards to adhere the two multilayer circuit boards to each other. Therefore, a combined multilayer circuit board is almost finished.

With reference to FIG. 9, the (c) act drills multiple through holes through the combined multilayer circuit board and then electroplates peripheries defining the through holes to form multiple outer conductive vias (72). Each outer conductive via (72) electronically interconnects to the conducting wires (13, 23) and the conductive layers (60) in the two multilayer circuit boards.

The (d) act etches patterns on the conductive layers (60) and coats an insulating lacquer layer (90) on a portion of the patterned conductive layers (60) to finish the combined multilayer circuit board. With further reference to FIGS. 10 and 11, the patterned conductive layers (60) become circuits and the patterned conductive layer un-coated with the insulating lacquer layer (90) become contacts (61).

With further reference to FIG. 12, a second embodiment of the manufacturing method in accordance with the present invention comprises mostly the same acts as the acts of the first embodiment of the manufacturing method. The second embodiment of the manufacturing method uses two single-layer FR4 printed circuit boards (10).

With further reference to FIG. 13, a third embodiment of the manufacturing method in accordance with the present invention comprises mostly the same acts as the acts of the first embodiment of the manufacturing method. The third embodiment of the manufacturing method uses two single-layer cooper plate printed circuit boards (20).

With further reference to FIG. 14, the fourth embodiment of the manufacturing method in accordance with the present invention comprises mostly the same acts as the acts of the first embodiment of the manufacturing method. The fourth embodiment of the manufacturing method uses three multilayer circuit boards. Two of the three multilayer circuit boards are fabricated by using two single-layer cooper plate printed circuit boards (20), and the other one multilayer circuit boards is fabricated by using single-layer FR4 printed circuit board (10). One of the multilayer circuit boards consisting of the single-layer cooper plate printed circuit board (20) is reversed. The multilayer circuit board consisting of the single-layer FR4 printed circuit board (10) is sandwiched in between the multilayer circuit board consisting of the single-layer cooper plate printed circuit boards (20).

With such a method, a combined multilayer circuit board is manufactured. The combined multilayer circuit board is not only a circuit board, but also a circuit board has multiple chips embedded in. The combined circuit board can be a motherboard, a printed circuit board or the like. Therefore, most of the passive elements are mounted in the combined circuit board. Furthermore, the combined multilayer circuit board manufactured by the method in accordance with the present invention provides more multi-function than the conventional multi-chips module but without lager size.

Even though numerous characteristics and advantages of the present invention have been set forth in the foregoing description, together with details of the structure and function of the invention, the disclosure is illustrative only. Changes may be made in detail, especially in matters of arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.

Claims

What is claimed is:

1. A method of manufacturing a combined multilayer circuit board having embedded chips comprising acts of:

(a) providing at least two multilayer circuit boards, wherein at least one of the multilayer circuit boards is fabricated by steps of

(a1) preparing a single-layer FR4 printed circuit board having multiple chip sections arranged in matrix, and each chip section having

a FR4 substrate;

multiple conducting wires formed on the FR4 substrate of each chip section;

an insulating coating coated on a portion of the multiple conducting wires; and

multiple contacts defined as the exposed portion of the multiple conducting wires;

(a2) attaching at least one chip to the corresponding chip section of the single-layer FR4 printed circuit board, wherein each chip is electronically connected to the contacts on the corresponding single-layer FR4 printed circuit board;

(a3) attaching a frame to the single-layer FR4 printed circuit board, wherein the frame has multiple enclosures corresponding to the chip sections on the single-layer FR4 printed circuit board to enclose the corresponding chip section and the corresponding chip;

(a4) attaching a semi-fluid glue sheet to the frame to cover the frame;

(a5) vacuum pressing a conductive layer on the semi-fluid glue sheet to fill inside of the enclosures with glue of the semi-fluid glue sheet to encapsulate the chips; and

(a6) forming multiple inner conductive vias by drilling multiple holes through the multilayer circuit board and then electroplating peripheries defining the holes to electronically connect the conducting wires to the conductive layer in the multilayer circuit board; and

at least one of the other multilayer circuit boards is fabricated by steps of

(b) combining the at least two multilayer circuit boards to form a combined multilayer circuit board, wherein the act (b) comprises steps of

(b1) reversing one of the multilayer circuit boards; and

(b2) vacuum pressing other multilayer circuit boards on the reversed multilayer circuit board with multiple glue layers, and each glue layer sandwiched in between the two multilayer circuit boards;

(c) forming multiple outer conductive vias by drilling multiple through holes through the combined multilayer circuit board and then electroplating peripheries defining the through holes to electronically interconnect the conducting wires and the conductive layers in the at least two multilayer circuit boards; and

(d) forming circuits and contacts on the combined multilayer circuit board by etching patterns on the conductive layers and coating an insulating lacquer layer on a portion of the patterned conductive layers.

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