Crolles Cedex
France
28
2013-04-18
20
2014-09-23
These are the the leading inventors for applications assigned to S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES:
S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES based in Crolles Cedex, FR has been assigned the rights to these inventions. The list includes both Pending Applications and Patent Grants:
THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS
#2 | 2013-02-14 ✅ Patent 8,842,945 granted on 2014-09-23Methods of forming three dimensionally integrated semiconductor systems including photoactive devices and semiconductor-on-insulator substrates
#3 | 2013-02-14 ✅ Patent 8,617,925 granted on 2013-12-31Methods of forming bonded semiconductor structures in 3D integration processes using recoverable substrates, and bonded semiconductor structures formed by such methods
#4 | 2013-02-14 ✅ Patent 8,728,863 granted on 2014-05-20Methods of forming bonded semiconductor structures including interconnect layers having one or more of electrical, optical, and fluidic interconnects therein, and bonded semiconductor structures formed using such methods
#5 | 2013-01-24 ✅ Patent 8,697,493 granted on 2014-04-15Bonding surfaces for direct bonding of semiconductor structures
#6 | 2012-10-04 ✅ Patent 8,716,105 granted on 2014-05-06Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
#7 | 2012-10-04 ✅ Patent 8,338,294 granted on 2012-12-25Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods
#8 | 2012-10-04METHODS OF FORMING BONDED SEMICONDUCTOR STRUCTURES, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS
#9 | 2012-08-23 ✅ Patent 8,975,165 granted on 2015-03-10III-V semiconductor structures with diminished pit defects and methods for forming the same
#10 | 2012-06-28 ✅ Patent 8,637,383 granted on 2014-01-28Strain relaxation using metal materials and related structures
#11 | 2012-06-21 ✅ Patent 8,575,001 granted on 2013-11-05Methods for directly bonding together semiconductor structures, and bonded semiconductor structures formed using such methods
#12 | 2012-04-05 ✅ Patent 8,133,806 granted on 2012-03-13Systems and methods for forming semiconductor materials by atomic layer deposition
#13 | 2012-04-05 ✅ Patent 8,486,192 granted on 2013-07-16Thermalizing gas injectors for generating increased precursor gas, material deposition systems including such injectors, and related methods
#14 | 2012-02-02 ✅ Patent 8,932,938 granted on 2015-01-13Method of fabricating a multilayer structure with circuit layer transfer
#15 | 2011-12-01 ✅ Patent 8,785,293 granted on 2014-07-22Adaptation of the lattice parameter of a layer of strained material
#16 | 2011-12-01 ✅ Patent 9,041,165 granted on 2015-05-26Relaxation and transfer of strained material layers
#17 | 2011-11-24METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING DIRECT BONDING OF SUBSTRATES
#18 | 2011-11-17THREE DIMENSIONAL STRUCTURES HAVING IMPROVED ALIGNMENTS BETWEEN LAYERS OF MICROCOMPONENTS
#19 | 2011-11-17 ✅ Patent 8,614,501 granted on 2013-12-24Method of producing a layer of cavities
#20 | 2011-11-03 ✅ Patent 8,507,332 granted on 2013-08-13Method for manufacturing components
#21 | 2011-09-29TEST METHOD ON THE SUPPORT SUBSTRATE OF A SUBSTRATE OF THE "SEMICONDUCTOR ON INSULATOR" TYPE
#22 | 2011-09-22 ✅ Patent 8,298,916 granted on 2012-10-30Process for fabricating a multilayer structure with post-grinding trimming
#23 | 2011-08-11METHOD OF PRODUCING A SILICON-ON-SAPPHIRE TYPE HETEROSTRUCTURE
#24 | 2011-08-11METHOD TO FABRICATE AND TREAT A STRUCTURE OF SEMICONDUCTOR-ON-INSULATOR TYPE, ENABLING DISPLACEMENT OF DISLOCATIONS, AND CORRESPONDING STRUCTURE
#25 | 2011-07-28PROCESS FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE
#26 | 2011-05-19 ✅ Patent 8,114,754 granted on 2012-02-14Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods
#27 | 2008-07-24 ✅ Patent 7,807,548 granted on 2010-10-05Process of forming and controlling rough interfaces
#28 | 2008-07-24 ✅ Patent 8,268,703 granted on 2012-09-18Surface roughening process
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