Electronic component device

Semiconductor device and production method therefor

Packaged microelectronic components

Lead-free solder alloy

Semiconductor device and semiconductor package containing the same

Low profile surface mount package with isolated tab

Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask

Semiconductor device with copper-tin compound on copper connector

Semiconductor device having conductive pads and a method of manufacturing the same

Plasma treatment for semiconductor devices

MULTI-CHIP MODULE CONNECTION BY WAY OF BRIDGING BLOCKS

Semiconductor packages utilizing leadframe panels with grooves in connecting bars

Method of manufacturing semiconductor device

Method for fabricating a semiconductor and semiconductor package

Embedded semiconductor die package and method of making the same using metal frame carrier

Semiconductor package having an over-temperature protection circuit utilizing multiple temperature threshold values

Packaged nano-structured component and method of making a packaged nano-structured component

Packaged semiconductor assemblies and methods for manufacturing such assemblies

Memory device, laminated semiconductor substrate and method of manufacturing the same

Enhanced capture pads for through semiconductor vias

Contoured package-on-package joint

Multi-solder techniques and configurations for integrated circuit package assembly

Integrated circuit device including a copper pillar capped by barrier layer and method of forming the same

Semiconductor device with conductive vias

Method and system for controlling chip inclination during flip-chip mounting

Integrated bondline spacers for wafer level packaged circuit devices

Semiconductor package having multi-phase power inverter with internal temperature sensor

NON-SOLDER MASK DEFINED COPPER PAD AND EMBEDDED COPPER PAD TO REDUCE PACKAGING SYSTEM HEIGHT

Microelectronic assembly with impedance controlled wirebond and reference wirebond

Laminate electronic device

Semiconductor device and manufacturing method thereof

Stacked dual-chip packaging structure and preparation method thereof

Semiconductor device having electrode pads arranged between groups of external electrodes

Control and driver circuits on a power quad flat no-lead (PQFN) leadframe

Power quad flat no-lead (PQFN) package having control and driver circuits

Integrated antennas in wafer level package

EPHEMERAL BONDING

Bond pad structure and method of manufacturing the same

Semiconductor device and method of confining conductive bump material with solder mask patch

Semiconductor device and method for manufacturing thereof

System in package manufacturing method using wafer-to-wafer bonding

Semiconductor device and method of making TSV interconnect structures using encapsulant for structural support

Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate

Wire bondable surface for microelectronic devices

Metal bump joint structure

Routing layer for mitigating stress in a semiconductor die

Packaging devices, methods of manufacture thereof, and packaging methods

Bump package and methods of formation thereof

Semiconductor device and production method therefor

Cylindrical embedded capacitors

Structures embedded within core material and methods of manufacturing thereof

Semiconductor module, MOS type solid-state image pickup device, camera and manufacturing method of camera

Semiconductor package with bonding wires of reduced loop inductance

Self-aligned protection layer for copper post structure

Semiconductor device and a method of manufacturing the same

Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs

Power quad flat no-lead (PQFN) package having bootstrap diodes on a common integrated circuit (IC)

Dual-leadframe multi-chip package

Semiconductor chip device with polymeric filler trench

Microelectronic assembly with impedance controlled wirebond and conductive reference element

Alkali silicate glass based coating and method for applying

Techniques for packaging multiple device components

Two-sided-access extended wafer-level ball grid array (eWLB) package, assembly and method

Stacked multi-chip integrated circuit package

Thermally enhanced package-on-package (PoP)

Power quad flat no-lead (PQFN) package in a single shunt inverter circuit

Open source power quad flat no-lead (PQFN) package

Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same

Embedded structures for package-on-package architecture

Use of electrical power multiplication for power smoothing in power distribution

Semiconductor device with stacked semiconductor chips

Localized high density substrate routing

Three dimensional integrated circuits stacking approach

Using collapse limiter structures between elements to reduce solder bump bridging

Power quad flat no-lead (PQFN) semiconductor package with leadframe islands for multi-phase power inverter

Method of mounting semiconductor chips, semiconductor device obtained using the method, method of connecting semiconductor chips, three-dimensional structure in which wiring is provided on its surface, and method of producing the same

Method of fabricating a wafer level chip scale package without an encapsulated via

Package process and package structure

Microelectronic structures having laminated or embedded glass routing structures for high density packaging

Method for producing multi-layer substrate and multi-layer substrate

Semiconductor package substrates having pillars and related methods

Method of fabricating semiconductor package structure

Direct multiple substrate die assembly

Processes for multi-layer devices utilizing layer transfer

Thermal dissipation through seal rings in 3DIC structure

Stacked-die including a die in a package substrate

Semiconductor device

Semiconductor device including semiconductor chip mounted on lead frame

Semiconductor device with dummy metal protective structure around semiconductor die for localized planarization of insulating layer

Semiconductor device including integrated passive device formed over semiconductor die with conductive bridge and fan-out redistribution layer

Integrated circuit, a chip package and a method for manufacturing an integrated circuit

Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier

Semiconductor packaging method using connecting plate for internal connection

Method for producing semiconductor device

Compliant printed circuit semiconductor package

Heat sinking and electromagnetic shielding structures

Integrated circuit device

Semiconductor package device having passive energy components

Semiconductor packages having warpage compensation

Solder interconnect with non-wettable sidewall pillars and methods of manufacture

Post passivation interconnect structures and methods for forming the same

Microelectronic packages with nanoparticle joining

Semiconductor device with protective layer over exposed surfaces of semiconductor die

Passive devices in package-on-package structures and methods for forming the same

Semiconductor device having low dielectric insulating film and manufacturing method of the same

Chip package and manufacturing method thereof

Techniques for reducing inductance in through-die vias of an electronic assembly

Radiation efficient integrated antenna

Electronic substrate, semiconductor device, and electronic device

Semiconductor device and semiconductor assembly with lead-free solder

Packaging methods and packaged devices

Extrusion-resistant solder interconnect structures and methods of forming

Coupling assembly of power semiconductor device and PCB and method for manufacturing the same

Semiconductor package with connecting plate for internal connection

Bridge interconnect with air gap in package assembly

Bondable top metal contacts for gallium nitride power devices

Direct injection molded solder process for forming solder bumps on wafers

Double solder bumps on substrates for low temperature flip chip bonding

Semiconductor device with pre-molding chip bonding

Methods and apparatus for package on package structures

Structure to increase resistance to electromigration

Bump structures for semiconductor package

Die underfill structure and method

Three dimensional (3D) fan-out packaging mechanisms

Power quad flat no-lead (PQFN) package

Stacked die power converter

Electronic system modules and method of fabrication

Electronic device and semiconductor device

Chip package and a method for manufacturing a chip package

Method for manufacturing a circuit board structure

Method of manufacturing a component comprising cutting a carrier

METHOD FOR MAKING A DOUBLE-SIDED FANOUT SEMICONDUCTOR PACKAGE WITH EMBEDDED SURFACE MOUNT DEVICES, AND PRODUCT MADE

Method for manufacturing a metal pad structure of a die, a method for manufacturing a bond pad of a chip, a die arrangement and a chip arrangement

Semiconductor device having a copper plug

Devices for metallization

Semiconductor package having protective layer with curved surface and method of manufacturing same

Method of manufacturing semiconductor device

Stacked dual chip package having leveling projections

Method of fabricating a package substrate

Mounted structure and manufacturing method of mounted structure

INTEGRATED CIRCUIT PACKAGE HAVING MEDIUM-INDEPENDENT SIGNALING INTERFACE COUPLED TO CONNECTOR ASSEMBLY

Pad sidewall spacers and method of making pad sidewall spacers

Contact pads with sidewall spacers and method of making contact pads with sidewall spacers

Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure

Bonded structures for package and substrate

Multi-chip module with multiple interposers

Semiconductor package having a recess filled with a molding compound

Semiconductor package for high power devices

Semiconductor device and method of manufacturing the same

Hybrid wiring board with built-in stopper, interposer and build-up circuitry

Package assembly and methods for forming the same

Interposer system and method

Apparatus, system, and method for wireless connection in integrated circuit packages

Controlled collapse chip connection (C4) structure and methods of forming

Semiconductor structures comprising a dielectric material having a curvilinear profile

Integrated circuit with a thermally conductive underfill and methods of forming same

Semiconductor device for preventing a progression of a crack in a solder layer and method of manufacturing the same

Microelectronic devices and methods for manufacturing microelectronic devices

Fluid storage and dispensing system including dynamic fluid monitoring of fluid storage and dispensing vessel

Integrated system and method of making the integrated system

Semiconductor device and programming method

Semiconductor device stack with bonding layer and wire retaining member

Semiconductor device and method of manufacturing the same

Chip package and a method for manufacturing a chip package

Metal cored solder decal structure and process

Embedded package security tamper mesh

Solder bump for ball grid array

Method of fabricating a chip package

SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF

Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics

Top exposed semiconductor chip package

Semiconductor device and manufacturing method thereof

Fabricating method of embedded package structure

Routing method for flip chip package and apparatus using the same

Electronic devices including two or more substrates electrically connected together and methods of forming such electronic devices

Diffusion barrier for surface mount modules

Production of adhesion structures in dielectric layers using photoprocess technology and devices incorporating adhesion structures

Repairing anomalous stiff pillar bumps

Bump structure for yield improvement

Electric device package comprising a laminate and method of making an electric device package comprising a laminate

CIS chips and methods for forming the same

Warpage control in the packaging of integrated circuits

Method and device for electrically contacting terminal faces of two substrates by laser soldering using a gaseous flux medium

Microelectronic packages having cavities for receiving microelectronic elements

Embedded integrated circuit package and method for manufacturing an embedded integrated circuit package

Semiconductor package with single sided substrate design and manufacturing methods thereof

Method of manufacturing a semiconductor device with a carrier having a cavity and semiconductor device

Semiconductor package and method of fabricating the same

Chip package and a method for manufacturing a chip package

Solder volume compensation with C4 process

Package on package devices and methods of packaging semiconductor dies

Redistribution layer (RDL) with variable offset bumps

Wafer-level device packaging

GaN power device with solderable back metal

Method of manufacturing a ball grid array substrate or a semiconductor chip package

Methods for flip chip stacking

Multilayer ceramic electronic device and method for manufacturing the same

Backside processing of semiconductor devices

Method of packaging a die

Stacked fan-out semiconductor chip

Semiconductor package and method of fabricating the same

Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods

Semiconductor device including cooler

Underfill material dispensing for stacked semiconductor chips

Method for manufacturing semiconductor package

Copper or copper alloy, bonding wire, method of producing the copper, method of producing the copper alloy, and method of producing the bonding wire

SUBSTRATE STRUCTURE, SEMICONDUCTOR PACKAGE AND METHODS OF FABRICATING THE SAME

Component and method of manufacturing a component using an ultrathin carrier

Semiconductor device and method of forming bump-on-lead interconnection

Chip package and method of manufacturing the same

Microelectronic flip chip packages with solder wetting pads and associated methods of manufacturing

Waveguide integration on laser for alignment-tolerant assembly

Mount board and electronic device

Semiconductor device capable of switching operation modes and operation mode setting method therefor

3DIC stacking device and method of manufacture

Package structures and methods for forming the same

Method for manufacturing a chip package

Semiconductor device and method of embedding thermally conductive layer in interconnect structure for heat dissipation

MICROELECTRONIC STRUCTURE HAVING A MICROELECTRONIC DEVICE DISPOSED BETWEEN AN INTERPOSER AND A SUBSTRATE

CHIP PACKAGES, CHIP ARRANGEMENTS, A CIRCUIT BOARD, AND METHODS FOR MANUFACTURING CHIP PACKAGES

Solder flow impeding feature on a lead frame

Package-in-packages and methods of formation thereof

Thermally enhanced semiconductor package

Semiconductor structure with thin film resistor and terminal bond pad

Lead Frame Packages and Methods of Formation Thereof

Assembly and production of an assembly

Stacked packaging improvements

Reconstituted wafer stack packaging with after-applied pad extensions

Electronic assembly with detachable components

Substrate structure and semiconductor package using the same

Carbon nanotube-solder composite structures for interconnects, process of making same, packages containing same, and systems containing same

Semiconductor device and method of forming an embedded SOP fan-out package

Semiconductor device apparatus and assembly with opposite die orientations

Thermally enhanced semiconductor package with conductive clip

Apparatus, system, and method for wireless connection in integrated circuit packages

Microelectronic assembly tolerant to misplacement of microelectronic elements therein

Integrated circuit packaging system with through silicon via and method of manufacture thereof

Bumpless build-up layer package design with an interposer

SUBSTRATE STRUCTURE AND PACKAGE STRUCTURE

Electronic device packages having bumps and methods of manufacturing the same

Embedded packages including a multi-layered dielectric layer and methods of manufacturing the same

Semiconductor package structure and method for making the same

Current sensing using a metal-on-passivation layer on an integrated circuit die

Multilayer electronic support structure with cofabricated metal core

Calibration kits for RF passive devices

Method of making a stacked microelectronic package

Fabrication method of semiconductor package

Electronic modules

Electric device package and method of making an electric device package

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FILM ASSIST AND METHOD OF MANUFACTURE THEREOF

Die edge contacts for semiconductor devices

Through-hole electrode substrate

Embedded semiconductive chips in reconstituted wafers, and systems containing same

Electronic device and method for production

CTE ADAPTION IN A SEMICONDUCTOR PACKAGE

Methods and apparatus of packaging semiconductor devices

Bump-on-lead flip chip interconnection

Reduced stress TSV and interposer structures

Power semiconductor device and method therefor

Semiconductor device and a method of manufacturing the same

Power electronic devices

Semiconductor device, inverter device provided with semiconductor device, and in-vehicle rotating electrical machine provided with semiconductor device and inverter device

Method for shaping a laminate substrate

Batch process for three-dimensional integration

Integrated circuit packaging system with substrate and method of manufacture thereof

Three-dimensional system-level packaging methods and structures

Reactive bonding of a flip chip package

Releasable buried layer for 3-D fabrication and methods of manufacturing

Package-in-Package for High Heat Dissipation Having Leadframes and Wire Bonds

MULTI-CORE WIRE

Substrate-less stackable package with wire-bond interconnect

Implementing decoupling devices inside a TSV DRAM stack

Semiconductor power module and method of manufacturing the same

TSV fabrication using a removable handling structure

Manufacturing method of substrate for a semiconductor package, manufacturing method of semiconductor package, substrate for a semiconductor package and semiconductor package

Multi-chip package with offset die stacking and method of making same

Integrated circuit apparatus, systems, and methods

Three-dimensional chip stack and method of forming the same

Wafer-level packaging mechanisms

Wire-based methodology of widening the pitch of semiconductor chip terminals

Semiconductor device

Package with metal-insulator-metal capacitor and method of manufacturing the same

Bonding wire for semiconductor

Semiconductor device and method of depositing underfill material with uniform flow rate

Bump structure for stacked dies

CHIP CONNECTION STRUCTURE AND METHOD OF FORMING

Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages

Protected solder ball joints in wafer level chip-scale packaging

Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with substrate contact

Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP

Semiconductor die and method of forming Fo-WLCSP vertical interconnect using TSV and TMV

Semiconductor device and method of forming penetrable film encapsulant around semiconductor die and interconnect structure

WSP DIE HAVING REDISTRIBUTION LAYER CAPTURE PAD WITH AT LEAST ONE VOID

WSP DIE WITH OFFSET REDISTRIBUTION LAYER CAPTURE PAD

Semiconductor package with stacked semiconductor chips

Semiconductor packages and methods of formation thereof

Cu pillar bump with electrolytic metal sidewall protection

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

Method of fabricating a power semiconductor chip package

Thermally enhanced electronic package