Ming Sun

Pedestrian sensor assistance in a mobile device during typical device motions

User-specific learning for improved pedestrian motion modeling in a mobile device

Methods and configuration for manufacturing flip chip contact (FCC) power package

Wafer level chip scale package and process of manufacture

Method and apparatus for ultra thin wafer backside processing

Multi-layer lead frame package and method of fabrication

Method for making solder-top enhanced semiconductor device of low parasitic packaging impedance

Method and system for determining parameters of sinusoidal signals

Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers

WAFER-LEVEL CHIP SCALE PACKAGING OF METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT-TRANSISTORS (MOSFET'S)

Method of Making a Low Profile Flip Chip Power Module

Method and System for Estimating and Tracking Frequency and Phase Angle of 3-Phase Power Grid Voltage Signals

Multi-layer lead frame package and method of fabrication

Vertically packaged MOSFET and IC power devices as integrated module using 3D interconnected laminates

Wafer level chip scale package and process of manufacture

Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers

Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates

Method and apparatus for ultra thin wafer backside processing

Compact co-packaged semiconductor dies with elevation-adaptive interconnection plates

Conductive clip for semiconductor device package

DFN semiconductor package having reduced electrical resistance

Semiconductor package having a bridged plate interconnection

Dual flat non-leaded semiconductor package

Semiconductor package having a bridge plate connection

Wafer level chip scale package and process of manufacture

Compact inductive power electronics package

Compact power semiconductor package and method with stacked inductor and integrated circuit die

Wafer level chip scale packaging

Solder-top enhanced semiconductor device for low parasitic impedance packaging

CO-PACKAGED HIGH-SIDE AND LOW-SIDE NMOSFETS FOR EFFICIENT DC-DC POWER CONVERSION

Method of forming ultra thin chips of power devices

Chip scale power converter package having an inductor substrate

Method of making semiconductor package with plated connection

Flip chip contact (FCC) power package

Method and apparatus for ultra thin wafer backside processing

Low profile flip chip power module and method of making

High current semiconductor power device SOIC package

Method of fabricating a semiconductor device employing electroless plating

Structure and method for self protection of power device

Power MOSFET wafer level chip-scale package

Gold/silicon eutectic die bonding method

Semiconductor package having a bridged plate interconnection

Multi-die DC-DC boost power converter with efficient packaging

Semiconductor package having dimpled plate interconnections

Flip chip mounted semiconductor device package having a dimpled leadframe

Gold/silicon eutectic die bonding method

Common drain dual semiconductor chip scale package and method of fabricating same

Semiconductor package having improved thermal performance

Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backside

Packages for electronic devices implemented with laminated board with a top and a bottom patterned metal layers

Wafer-level method for metallizing source, gate and drain contact areas of semiconductor die

Semiconductor package having plate interconnections

Wafer level bumpless method of making a flip chip mounted semiconductor device package

Semiconductor package with plated connection

Flip chip contact (FCC) power package

DFN semiconductor package having reduced electrical resistance

Dual flat non-leaded semiconductor package