Wolfspeed, Inc.

Surface Processing of Semiconductor Workpieces

Electrical discharge machining processing for semiconductor workpiece

Hybrid seed structure for crystal growth system

Off axis laser-based surface processing operations for semiconductor wafers

Laser-based surface processing for semiconductor workpiece

Additives for Grinding Semiconductor Workpieces

Two Component Chemical Mechanical Polishing

Grind Wheel Design for Low Edge-Roll Grinding

Fill-in planarization system and method

DEVICE HAVING A RATE OF CURRENT CHANGE LIMITER AND PROCESS OF IMPLEMENTING THE SAME

Multi-scale autoencoders for semiconductor workpiece understanding

Laser-based processing for semiconductor wafers

Laser edge shaping for semiconductor wafers

Improved Thermal and Electrical Conductivity Between Metal Contacts

LARGE DIAMETER SILICON CARBIDE WAFERS

SILICON CARBIDE THERMAL BRIDGE INTEGRATED ON A LOW THERMAL CONDUCTIVITY SUBSTRATE AND PROCESSES IMPLEMENTING THE SAME

NONDESTRUCTIVE CHARACTERIZATION FOR CRYSTALLINE WAFERS

Field Reducing Structures for Nitrogen-Polar Group III-Nitride Semiconductor Devices

High Power Multilayer Module Having Low Inductance and Fast Switching for Paralleling Power Devices

Metal Nitride Core-Shell Particle Die-Attach Material

Compact power module

OPTIMIZATION OF POWER MODULE PERFORMANCE VIA PARASITIC MUTUAL COUPLING

INTEGRATED PASSIVE DEVICES (IPD) HAVING A BASEBAND DAMPING RESISTOR FOR RADIOFREQUENCY POWER DEVICES AND DEVICES AND PROCESSES IMPLEMENTING THE SAME

MULTIPLE TRANSPORT LEVEL TESTER SYSTEM

LASER-ASSISTED METHOD FOR PARTING CRYSTALLINE MATERIAL

Vertical power devices fabricated using implanted methods

GROUP III-NITRIDE HIGH-ELECTRON MOBILITY TRANSISTORS WITH BURIED P-TYPE LAYERS AND PROCESS FOR MAKING THE SAME

PACKAGE FOR POWER ELECTRONICS

DEVICE AND PROCESS FOR IMPLEMENTING SILICON CARBIDE (SIC) SURFACE MOUNT DEVICES

Power semiconductor device with reduced strain

Optimization of power module performance via parasitic mutual coupling

SEMICONDUCTOR DEVICE PACKAGES WITH EXPOSED HEAT DISSIPATING SURFACES AND METHODS OF FABRICATING THE SAME

PACKAGES WITH BACKSIDE MOUNTED DIE AND EXPOSED DIE INTERCONNECTS AND METHODS OF FABRICATING THE SAME

SEMICONDUCTOR DEVICE WITH SELECTIVELY GROWN FIELD OXIDE LAYER IN EDGE TERMINATION REGION

METHODS OF FORMING OHMIC CONTACTS ON SEMICONDUCTOR DEVICES WITH TRENCH/MESA STRUCTURES

GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING IMPROVED BREAKDOWN PERFORMANCE AND METHODS OF FORMING SUCH DEVICES

SEMICONDUCTOR DEVICES HAVING ON-CHIP GATE RESISTORS

GATE TRENCH POWER SEMICONDUCTOR DEVICES HAVING TRENCH SHIELDING PATTERNS FORMED DURING THE WELL IMPLANT AND RELATED METHODS

POWER MODULE

METHOD FOR REDUCING PARASITIC CAPACITANCE AND INCREASING PEAK TRANSCONDUCTANCE WHILE MAINTAINING ON-STATE RESISTANCE AND RELATED DEVICES

VERTICAL POWER DEVICES HAVING MESAS AND ETCHED TRENCHES THEREBETWEEN

Dual inline power module

Group III nitride-based monolithic microwave integrated circuits including static random access memory blocks with associated addressing and buffering circuits

Electronic device packages with internal moisture barriers

TRANSISTOR INCLUDING A DISCONTINUOUS BARRIER LAYER

Power module

RF AMPLIFIER DEVICES AND METHODS OF MANUFACTURING INCLUDING MODULARIZED DESIGNS WITH FLIP CHIP INTERCONNECTIONS AND INTEGRATION INTO PACKAGING

PACKAGED ELECTRONIC DEVICES HAVING TRANSIENT LIQUID PHASE SOLDER JOINTS AND METHODS OF FORMING SAME

SUPPORT SHIELD STRUCTURES FOR TRENCHED SEMICONDUCTOR DEVICES

SEMICONDUCTOR DEVICES HAVING GATE RESISTORS WITH LOW VARIATION IN RESISTANCE VALUES

Radio frequency transistor amplifiers having self-aligned double implanted source/drain regions for improved on-resistance performance and related methods

Semiconductor packages with increased power handling

Wide bandgap unipolar/bipolar transistor

Silicon carbide wafers with relaxed positive bow and related methods

Power semiconductor devices including a trenched gate and methods of forming such devices

Limiting failures caused by dendrite growth on semiconductor chips

Gate trench power semiconductor devices having improved deep shield connection patterns

Group III-nitride high-electron mobility transistors with a buried metallic conductive material layer and process for making the same

EDGE TERMINATION STRUCTURES FOR SEMICONDUCTOR DEVICES

Edge termination for power semiconductor devices and related fabrication methods

INTEGRATED POWER MODULE

Power module having an elevated power plane with an integrated signal board and process of implementing the same

Packaged semiconductor devices, and package molds for forming packaged semiconductor devices

DEVICE DESIGN FOR SHORT-CIRCUIT PROTECTION OF TRANSISTORS

Compact power module

Transistor with ohmic contacts

Transistor device structure with angled wire bonds

POWER SEMICONDUCTOR DEVICES INCLUDING MULTIPLE GATE BOND PADS

Vertical power devices fabricated using implanted methods

Semiconductor device incorporating a substrate recess

Arrangements of power semiconductor devices for improved thermal performance

Circuits and methods for controlling bidirectional CLLC converters

Compensation of trapping in field effect transistors

Encapsulation stack for improved humidity performance and related fabrication methods

Semiconductor devices having asymmetric integrated gate resistors for balanced turn-on/turn-off behavior

Vertical semiconductor device with improved ruggedness

Reduced optical absorption for silicon carbide crystalline materials

Integrated passive device (IPD) components and a package and processes implementing the same

Device and process for fault detection of a power device

MULTILAYER ENCAPSULATION FOR HUMIDITY ROBUSTNESS AND RELATED FABRICATION METHODS

Field effect transistors with modified access regions

FIELD EFFECT TRANSISTOR WITH SELECTIVE CHANNEL LAYER DOPING

FIELD EFFECT TRANSISTOR WITH SELECTIVE MODIFIED ACCESS REGIONS

GROUP III-NITRIDE TRANSISTORS WITH BACK BARRIER STRUCTURES AND BURIED P-TYPE LAYERS AND METHODS THEREOF

Circuits and group III-nitride high-electron mobility transistors with buried p-type layers improving overload recovery and process for implementing the same

CIRCUITS AND GROUP III-NITRIDE TRANSISTORS WITH BURIED P-LAYERS AND CONTROLLED GATE VOLTAGES AND METHODS THEREOF

High power multilayer module having low inductance and fast switching for paralleling power devices

Gallium Nitride high-electron mobility transistors with p-type layers and process for making the same

Power module having electrical interconnections using mechanical fittings and process of implementing the same

High output power density radio frequency transistor amplifiers in flat no-lead overmold packages

Field effect transistor with multiple stepped field plate

Drain and/or gate interconnect and finger structure

Power component configured for improving partial discharge performance and system and process of implementing the same

Trench bottom shielding methods and approaches for trenched semiconductor device structures

Semiconductor devices having gate resistors with low variation in resistance values

Power semiconductor device with reduced strain

Integrated power module

Packaged electronic devices having dielectric substrates with thermally conductive adhesive layers

Radio frequency transistor amplifiers having widened and/or asymmetric source/drain regions for improved on-resistance performance

Devices incorporating stacked bonds and methods of forming the same